➀ Memory manufacturers are competing to win over server operating system developers; ➁ Samsung is collaborating with Red Hat; ➂ SK Hynix appears to be aiming to win over the entire ecosystem.
Recent #CXL news in the semiconductor industry
➀ CXL consortium showcased advancements at FMS 2024, including new specifications and product demonstrations. ➁ SK hynix introduced a 128 GB CMM-DDR5 CXL memory module and a Heterogeneous Memory Software Development Kit (HMSDK). ➂ Marvell announced a new CXL product line, Structera, featuring compute accelerators and memory expansion controllers.
1. Marvell introduces Structera brand CXL 2.0 memory expansion and acceleration products with DDR4 DRAM recycling capability. 2. The products enable terabytes of memory to be added to general-purpose servers and address high-capacity memory applications. 3. Structera A 2504 and X 2404/X 2504 products support inline LZ4 compression/decompression and AES-XS 256-bit encryption.
1. Fadu will own and sell the CXL switch chip developed by its subsidiary Eeum; 2. Eeum CEO Jinki Han will define the hardware model and architecture of the chip; 3. Fadu will take over the register transfer level coding and oversee production and sale.
1. The article discusses the importance of PCIe and CXL technologies in modern computing infrastructures, highlighting their role in supporting high data transfer rates essential for AI/ML training and big data analytics. 2. It covers the recent webinar sponsored by Alphawave Semi, focusing on the challenges and advancements in optical interfaces and the need for collaborative innovation. 3. The article also explores the benefits of Linear Pluggable Optics (LPO) and energy-efficient accelerator cards in enhancing data center performance and scalability.
➀ Logic Fruit Technologies has released a new High-Speed Interface IP stack;
➁ The stack includes PCIe Gen6 Controller IP, PCIe Gen6 PHY IP, and CXL 3 Controller IP;
➂ The solutions ensure seamless data transfer and reliability for advanced computing applications.
➀ Panmnesia has launched a CXL-based GPU Memory Expansion Kit; ➁ The kit consists of CXL-GPUs and CXL-Memory Expanders; ➂ It can expand GPU internal memory capacity from tens of gigabytes to terabytes, reducing AI infrastructure costs.
➀ Compute Express Link (CXL) technology is expected to move from a niche to mainstream use in 2025; ➁ CXL's support for memory expansion is a significant driver, with various server and memory solutions now available; ➂ CXL 2.0 and future generations of PCIe/CXL will enable more advanced use cases like switching and dynamic memory allocation.
➀ Marvell's Structera A memory controller with 16 ARM cores is unveiled, showcasing its capabilities for CXL Type-3 memory expansion; ➁ The device is designed to enhance system compute and memory capacity, with potential for repurposing DDR4 DIMMs; ➂ The inclusion of ARM Neoverse V2 cores suggests high-performance applications beyond low-scale-out CPU cores.
➀ The CXL 3.2 specification has been officially released by the CXL consortium, focusing on optimizing the monitoring and management of CXL memory devices and enhancing their functionality for operating systems and applications.
➁ The specification also extends security through Trusted Security Protocol (TSP) and ensures full backward compatibility with previous CXL specifications.
➂ The CXL technology is designed for high-performance data center servers, allowing processor modules to share memory and providing low-latency interconnect paths for memory access and communication between host processors and devices that need shared memory resources.
➀ The rise of artificial intelligence and machine learning applications requires expanded memory capacity and data bandwidth;
➁ The CXL interface, based on PCIe, aims to provide low-latency, high-bandwidth connections for efficient memory sharing between devices such as CPUs, GPUs, and accelerators;
➂ The CXL interface allows Flash to overcome the semantic wall between DRAM and Flash, providing high capacity and low-cost memory.
➀ Panmnesia, a Korean startup focusing on CXL switch chips and CXL IP, has raised $60 million in Series A funding, valuing the company at $250 million. The funds will be used for the completion of the CXL 3.1 switch chip manufacturing, advancement of CXL IP, and global IT company collaborations. ➁ Founded in 2022, Panmnesia is led by CEO Myoungsoo Jung, a professor at KAIST, and includes Masters and PhD researchers. ➂ The round was led by InterVest and included new investors like Korea Investment Partners and existing investors such as Daekyo Investment.
➀ Lenovo showcases a new server, the ThinkSystem SR860 V3, with 128x 128GB DDR5 DIMMs and CXL memory technology; ➁ The server leverages Astera Labs Leo CXL controllers to achieve massive memory capacity; ➂ The system supports up to 16TB of memory and can accommodate four double-width GPUs.
➀ Meta has introduced the AMD EPYC Turin processors into its Yosemite v4 server platform; ➁ The Yosemite v4 is Meta's latest scale-out chassis architecture, designed for high-performance computing; ➂ The integration of AMD EPYC Turin and CXL support in Yosemite v4 is expected to enhance system capabilities and performance.
➀ Inventec and Astera Labs have showcased a 96x DDR5 DIMM memory shelf at the OCP Summit 2024; ➁ The shelf connects to an 8-way Intel Xeon 6 Granite Rapids-SP server with 128x DDR DIMM slots, offering a total of 224 DIMMs; ➂ The setup is designed for scale-up server applications, providing tens of TBs of memory in a single server.
➀ Intel launches the 128-core Xeon 6 performance core processor series; ➁ The new processors feature a massive 504MB L3 cache and support MRDIMM for increased memory bandwidth; ➂ CXL 2.0 support allows for memory sharing and pooling, enhancing system performance; ➃ The Flat memory mode unifies DRAM and CXL memory, improving memory management efficiency.
➀ The transition of AI servers from HBM to CXL technologies; ➁ The importance of high-speed memory bandwidth in AI servers; ➂ The rise of HBM technology to overcome 'memory wall' issues; ➃ Market dominance of HBM suppliers like SK Hynix, Samsung, and Micron; ➄ The impact of new interconnect technologies like CXL and MCR/MDIMM on AI server performance; ➅ Micron's product roadmap and Rambus' interconnect solutions; ➆ The significance of SPD EEPROMs in DDR5 memory systems.
➀ Saniffer releases updated version 11.1 of its PCIe5&6.0, CXL, NVMe/NVMoF, SSD, NAND, DDR5, 800GE test technology and tool whitepaper; ➁ PCIe Gen6 NVMe SSD testing begins, with focus on E3.S or E1.S interfaces; ➂ FMS 2024 participation summary with 3505 attendees, including 12 Chinese companies; ➃ PCIe Gen6 interoperability issues identified and scheduled for further testing in October; ➄ AI infrastructure hardware diagnosis, analysis, and testing added to whitepaper, including AI training and inference architectures; ➅ 800G/1.6T optical module development and testing advancements driven by AI and data center demands; ➆ Nvidia starts certifying 1.6T optical modules in June 2024.
➀ YEESTOR showcased its CXL SSD solutions at FMS 2024, addressing the 'storage wall' issue with innovative CXL technology. ➁ The company demonstrated a range of storage solutions including PCIe SSD controllers and UFS controllers, tailored for AI, mobile, cloud computing, and more. ➂ YEESTOR also highlighted its advancements in automotive, industrial, and enterprise-grade storage solutions, emphasizing its commitment to innovation and market diversification.
1. JEDEC has released JESD405-1B, a standard for CXL memory module labels, detailing information like memory type, protocol revision, and capacity. 2. The standard supports SNIA EDSFF form factors E1.S and E3.S, and includes connector and I/O configuration details. 3. JESD405-1B, along with JESD317A, aims to support and expand the CXL market by ensuring multiple sourcing options for CMMs.