➀ Kyocera Pegatron and SMART showcased a prototype demonstrating CXL memory accessed remotely via optical connections at Computex 2025;

➁ The setup utilized SMART's CXL memory module, Kyocera's PCIe-to-optical converter, and MTP/MPO fiber cables, enabling dynamic memory allocation in distributed systems;

➂ The technology highlights future applications in AI clusters and aligns with upcoming PCIe Gen6 advancements, signaling progress toward optical co-packaging solutions.

➀ Panmnesia launched the Link Solution product line for AI infrastructure, encompassing hardware, silicon IPs, network topology, and software;

➁ The solution reduces communication overhead, enhances system performance, and supports diverse devices/interconnects for flexible AI workload adaptation;

➂ Panmnesia collaborates with industry consortia (CXL, UALink, OCP, PCI-SIG) to advance composable architectures for GPUs, AI accelerators, and memory modules.

➀ Panmnesia, a Korean CXL specialist, launched a full-stack HPC system using CXL 3.x switches and IP, enabling flexible resource scaling and enhanced parallel computing performance;

➁ The composable hardware architecture allows independent scaling of compute and memory nodes via CXL switches, reducing costs by eliminating redundant resources;

➂ The software stack replaces network-based communication with CXL memory sharing, cutting latency by 44% in a fluid dynamics simulation demonstration.

➀ This article provides a quick guide on how to display CXL memory in a system;

➁ It explains the process of identifying CXL memory devices using various commands like lscpu, lspci, and numactl;

➂ The guide also covers how to view the CXL memory topology and latencies using lstopo and ndctl.

➀ Logic Fruit Technologies has released a new High-Speed Interface IP stack;

➁ The stack includes PCIe Gen6 Controller IP, PCIe Gen6 PHY IP, and CXL 3 Controller IP;

➂ The solutions ensure seamless data transfer and reliability for advanced computing applications.

➀ The CXL 3.2 specification has been officially released by the CXL consortium, focusing on optimizing the monitoring and management of CXL memory devices and enhancing their functionality for operating systems and applications.

➁ The specification also extends security through Trusted Security Protocol (TSP) and ensures full backward compatibility with previous CXL specifications.

➂ The CXL technology is designed for high-performance data center servers, allowing processor modules to share memory and providing low-latency interconnect paths for memory access and communication between host processors and devices that need shared memory resources.

➀ The rise of artificial intelligence and machine learning applications requires expanded memory capacity and data bandwidth;

➁ The CXL interface, based on PCIe, aims to provide low-latency, high-bandwidth connections for efficient memory sharing between devices such as CPUs, GPUs, and accelerators;

➂ The CXL interface allows Flash to overcome the semantic wall between DRAM and Flash, providing high capacity and low-cost memory.