➀ Marvell showcased its first 2nm silicon wafer IP designed for next-generation AI and cloud infrastructure;
➁ The wafer, produced using TSMC's 2nm process, is part of Marvell's platform for developing custom XPU, switches, and other technologies to enhance cloud service providers' global operations;
➂ Marvell's platform strategy focuses on developing a comprehensive semiconductor IP product portfolio, including SerDes, chip-to-chip interconnects, advanced packaging technologies, and custom high-bandwidth memory (HBM) computing architectures;
➃ Marvell also introduced 3D synchronous bidirectional I/O with speeds up to 6.4 Gbits/second for connecting vertically stacked chips within a single die;
➄ The company expects custom silicon to account for about 25% of the accelerated computing market by 2028;
➅ Marvell's 2nm platform is tailored for TSMC's 2nm process technology and includes technologies for developing cloud-optimized accelerators, Ethernet switches, and digital signal processors;
➆ Marvell's custom HBM computing architecture allows XPU to achieve higher computing and memory density;
➇ The new architecture enhances XPU performance by serializing and accelerating the I/O interface between the AI computing accelerator silicon wafer and the HBM wafer;
➈ Marvell's custom AI accelerator architecture integrates XPU computing silicon wafers, HBM, and other chips with Marvell's 3D SiPho engine on the same substrate;
➉ Marvell has been a pioneer in changing interconnect technology, focusing on improving the performance, scalability, and cost-effectiveness of accelerated infrastructure.