➀ The webinar discusses challenges in functional ECO (Engineering Change Order) for mixed-signal ASIC designs across smartphones, automotive, and IoT applications;

➁ Easy-Logic Technology presents specialized algorithms and methodologies to optimize ECO processes impacted by analog-digital integration and tight timelines;

➂ Their decade-long expertise addresses complex scenarios like iterative ECO cycles, RTL/netlist co-modification, and post-test chip revisions.

➀ Cyient Semiconductor partners with MIPS to develop domain-optimized ASICs for real-time, safety-critical applications, power delivery, and compute efficiency.

➁ Collaboration aims to integrate embedded intelligence with advanced power architectures on scalable open platforms to address performance challenges in edge-to-cloud systems.

➂ Target applications include motor drive control, intelligent power management, and safety-critical systems, offered as ASSP or ASIC solutions.

➀ ICsense, Europe's leading IC design company, reported record revenue exceeding €20 million for the fiscal year ending March 31, driven by strong ASIC sales and operational efficiency;

➁ The company achieved double-digit operational profit growth, attributed to successful project execution and recurring revenue from ASIC products;

➂ ICsense emphasized its focus on expanding ASIC solutions in automotive, medical, and industrial markets while increasing R&D investments for future growth.

➀ Creonic launches a new oFEC codec IP core for next-gen optical and high-speed communication systems;

➁ The IP core supports both ASIC and FPGA configurations, offering flexibility and scalability;

➂ Enhances Creonic's portfolio for advanced networking solutions in telecommunications and HPC applications.

➀ Siemens Digital Industries Software launches Questa One suite to address declining first-time silicon success rates (14% for ASIC, 13% for FPGA) through AI-powered verification;

➀ The suite includes four tools accelerating simulation, fault analysis, and stimulus-free verification, claiming 50x faster test generation and 48x fault simulation improvements;

➂ Integrated with Tessent technologies and Veloce systems, it supports 3D-IC, chiplets, and software-defined architectures, with early adopters reporting significant productivity gains.

➀ xAI's latest ASIC, not the widely known Dojo, is a new chip codenamed 'X1' designed specifically for LLM training.

➁ The chip will be produced using TSMC's most advanced 3nm N3 process, with an initial annual output of about 300,000 chips, of which Broadcom has received the order.

➂ The 'X1' chip is designed to enhance computational efficiency, featuring larger capacity SRAM and a dedicated Data Engine to reduce data movement energy consumption during model training and increase throughput.

➀ Aion Silicon (formerly Sondrel) rebrands to focus on advanced SoC and ASIC solutions;

➁ Leverages decades of expertise to address complex semiconductor development challenges;

➂ Introduces new leadership team and vision to enhance customer-centric chip design services.

➀ KeyASIC, a leading ASIC design services company, has partnered with AnySilicon;

➁ The collaboration aims to expand KeyASIC's marketing reach;

➂ Access to AnySilicon's extensive network of potential customers seeking ASIC design solutions is provided.

➀ Hailo, a pioneering chipmaker of edge AI processors, has selected Avnet ASIC as its silicon channel partner for future chip production.

➁ Avnet ASIC is a leading provider of ASIC and SoC full turnkey solutions and a business division of Avnet Silica.

➂ The collaboration is for future chips to be produced using TSMC's silicon technology.

➀ Cadence has launched Conformal AI Studio, an advanced AI tool designed to tackle the challenges of increasing SoC design complexity.

➁ Key features include distributed Boolean logic equivalence checking, automated functional ECO generation, and low-power static signoff tools.

➂ Early adopters like MediaTek have reported significant improvements in productivity, including 83% smaller ECO patches and over 100X faster power-state-table analysis, demonstrating its potential for applications in AI infrastructure, hyperscalers, and mobile devices.

➀ Pragmatic Semiconductor and Electronics Weekly are hosting a webinar on the next-gen FlexIC design platform.

➁ The webinar is aimed at IC Designers, ASIC Engineers, and R&D professionals.

➂ It will cover the capabilities of the Pragmatic FlexIC Platform Gen 3, including rapid design and manufacturing of flexible mixed-signal ASICs.

➀ Zero ASIC has launched PlatypusTM, the world's first open-standard eFPGA IP product;

➁ Platypus features 100% open and standardized FPGA architectures;

➂ It also includes 100% open source FPGA bitstream formats.

➀ Pragmatic Semiconductor introduces the Pragmatic FlexIC Platform Gen 3, a next-generation mixed-signal flexible ASIC design platform;

➁ The platform offers a 10x digital power and 3x digital area improvement compared to the previous generation;

➂ The platform includes a process design kit (PDK) compatible with standard electronic design tools.

➀ AONDevices, a leader in super-low-power, high-accuracy edge AI solutions, has announced a strategic partnership with Faraday Technology Corporation.

➁ The collaboration aims to enhance AONDevices' production capabilities for its advanced AI processors.

➂ Faraday Technology brings its comprehensive manufacturing expertise to the partnership.

➀ CAST today announced a new IP core that implements the SNOW-V stream cipher algorithm;

➁ The core is designed to meet the security and performance demands of modern communication systems;

➂ It is available for ASICs or FPGAs and is believed to be the first commercial offering of its kind.

➀ Samsung Electronics' 4nm advanced process yield has approached 80% and recently received ASIC foundry orders from Chinese companies.

➁ The new management team has adjusted the strategy, no longer chasing the forefront competition, and focusing on winning customers with high yield.

➂ The popularity of the AI development platform DeepSeek has ignited the enthusiasm of Chinese technology companies to develop AI ASICs, with Samsung's price and capacity advantages becoming a key driving force for orders.

➀ Arm is reported to be planning to sell proprietary chips, with Meta being one of its first customers.

➁ The move is driven by the need for hyperscalers to use ASICs in datacentres to avoid high costs associated with Nvidia GPUs.

➂ Arm's recent trial with Qualcomm highlighted its CEO's strategy document, which included plans for Arm to build its own chips.

➀ EnSilica has been awarded £10.38 million over three years from the UK Space Agency's C-LEO programme.

➁ The funding will support the development of a chip family for future satellite broadband user terminals.

➂ The terminals will connect with various satellite constellations and utilize advanced semiconductor technology.