➀ The organizers of this year's Design and Verification Conference & Exhibition Europe (DVCon Europe) have announced the deadline for abstracts for engineering papers and tutorials for this year's event.
➁ Abstracts need to be submitted by 22 April, with full engineering and research papers required by 30 June.
➂ DVCon Europe will be hosted by Accellera Systems Initiative and will take place at the Holiday Inn Munich, Germany from 14 to 15 October.
➀ Pragmatic Semiconductor and Electronics Weekly are hosting a webinar on the next-gen FlexIC design platform.
➁ The webinar is aimed at IC Designers, ASIC Engineers, and R&D professionals.
➂ It will cover the capabilities of the Pragmatic FlexIC Platform Gen 3, including rapid design and manufacturing of flexible mixed-signal ASICs.
➀ Summary of various EDA tools for analog circuit design, including schematic design, simulation, SPICE model generation, transistor characteristics simulation, layout design, parasitic parameter extraction, LVS, IR-drop analysis, DRC, post-layout simulation, and mixed-signal simulation.
➁ Comparison of domestic and foreign manufacturers, highlighting the leading role of Cadence, Synopsys, and Mentor in the global market and the rapid growth of domestic companies like Hua Da Ji Tian and Guolun Electronics.
➂ Discussion on the challenges and opportunities in the analog chip design field, with a focus on AI-driven automation design and the construction of a domestic process ecosystem.
➀ Synopsys extends its Virtualizer IP suite to Arm hardware, enabling direct execution of virtual prototypes on Arm-based machines.
➁ The Native Element feature reduces boot times for Android from 20 minutes to tens of seconds.
➂ The tool supports hybrid emulation, combining virtual prototyping with hardware-assisted verification (HAV) for improved performance.
➀ The article discusses the evolution of semiconductor architecture from planar transistors to FinFETs and now to Gate-All-Around (GAA) technology.
➁ GAAFET, with its wider sheets, offers improved drive current and performance, and better electrostatic characteristics compared to FinFETs.
➂ The transition to GAA requires rethinking the physical design process, including vertical integration and optimized routing strategies.
➃ Innovative power delivery networks and advanced EDA tools are crucial for maintaining power integrity and stability.
➄ GAA technology presents opportunities to optimize power, performance, and area (PPA) in semiconductor designs.
➅ Challenges such as cost, complexity, and manufacturing issues are addressed through DFM tools and advanced verification methods.
