➀ Mach42的发现平台利用机器学习创建一个代理模型，以实现更快的电路设计探索，而无需进行完整的SPICE模拟。
➁ 平台的目标是达到90%的准确率，允许快速迭代，同时保留在最终确认时进行完整准确性的选项。
➂ Mach42正在与Cadence合作开发Spectre，并计划开发Verilog-A模型，这可能会显著增强模拟-数字设计验证。
Recent #Cadence news in the semiconductor industry
➀ The automotive industry is rapidly evolving towards intelligent, connected, and autonomous vehicles with SoC technology; ➁ Chiplet-based architectures offer modular, scalable, and customizable solutions for automotive SoC design; ➂ Cadence provides tools and frameworks to enhance the design process and ensure safety, performance, and reliability.
➀ The manual process of migrating DRAM chips between process nodes is a challenge; ➁ Cadence's Virtuoso Studio tools enable AI-driven design migration; ➂ AI-powered flow automates the migration process, improving productivity and reducing engineering effort.
➀ The rise in hearing loss among young adults and the global need for better hearing aids; ➁ The FDA's authorization for Apple AirPods Pro to be sold over the counter as a hearing aid; ➂ The trend towards AI-driven personalization in hearing aids and the role of Cadence Tensilica in supporting this technology.
➀ Intel and Cadence collaborate to advance the UCIe standard, focusing on multi-die design and interoperability. ➁ The collaboration aims to address technical challenges in UCIe compliance and pre-silicon interoperability. ➂ The white paper details the strategies and technical advancements in building an open chiplet ecosystem.
➀ The automotive industry's demand for high-capacity, high-speed storage solutions has led to the adoption of SPI Octal DDR NAND Flash, which presents unique verification challenges. ➁ Traditional verification models for NOR Flash are inadequate for simulating the complex architecture of Octal SPI NAND devices. ➂ Cadence, in collaboration with Winbond, has developed an enhanced SPI NAND Flash Memory Model to address these challenges, ensuring reliable performance in automotive applications.
1. PAM4 SerDes technology significantly enhances data throughput and power efficiency for AI and data center applications; 2. The technology supports various reach requirements, from long to short, ensuring reliable and high-speed data transmission; 3. Cadence's advanced SerDes solutions and involvement in the Ultra Ethernet Consortium highlight ongoing innovations in Ethernet technology.
1. Cadence introduces the Janus NoC IP to enhance its system IP portfolio, addressing complex interconnect challenges in SoCs. 2. The Janus NoC provides scalable architecture, efficient communication, and supports dynamic configurations for multi-chip and chiplet designs. 3. It leverages Cadence's extensive software and hardware offerings, ensuring high performance, power efficiency, and area optimization.
1. Timing closure is critical for final chip design sign-off, especially with increasing interconnect resistance and capacitance parasitics. 2. Analog design lacks automation and heavily relies on handcrafted layouts and hand-estimated parasitics, leading to more post-layout issues. 3. The Cadence Quantus Insight Solution aims to accelerate expert designer insight and suggested fixes before long-cycle layout changes and re-simulation.
➀ Cadence has launched Conformal AI Studio, an advanced AI tool designed to tackle the challenges of increasing SoC design complexity.
➁ Key features include distributed Boolean logic equivalence checking, automated functional ECO generation, and low-power static signoff tools.
➂ Early adopters like MediaTek have reported significant improvements in productivity, including 83% smaller ECO patches and over 100X faster power-state-table analysis, demonstrating its potential for applications in AI infrastructure, hyperscalers, and mobile devices.
➀ Jayashankar Narayanankutty, Cadence Design Systems的销售总监，讨论了公司与印度政府合作的计划如何推动其业务增长，特别是在初创公司领域。
➁ Cadence通过灵活的商业模式为不同阶段的初创企业提供支持，包括提供免费或延迟支付的EDA工具，以帮助解决资金和技术挑战。
➂ Cadence正在投资于AI驱动的设计工具和3D集成电路技术，这可能成为印度在半导体行业取得领先地位的机会。
➀ Cadence announces its plan to acquire Secure-IC, a leader in embedded security IP platforms.
➁ The acquisition aims to enhance Cadence's existing portfolio with Secure-IC's advanced security solutions and tools.
➂ Financial details of the deal were not disclosed.
➀ Introduction to Cadence Virtuoso; ➁ Key features and capabilities; ➂ Importance for engineers and designers
➀ Cadence has introduced a new system chiplet based on Arm; ➁ The article delves into the motivations behind this move; ➂ The Briefing series provides further insights.
➀ Cadence Design Systems announced the appointment of Moshe Gavrielov to its board of directors; ➁ The appointment will be effective from January 1, 2025; ➂ Gavrielov is currently a board member at NXP Semiconductors and Taiwan Semiconductor Manufacturing Company Ltd.
➀ MosChip selects Cadence's 5nm EDA tools for designing the HPC processor 'AUM' for C-DAC; ➁ MosChip is the first publicly traded fabless semiconductor company in India with over 25 years of experience in designing products and SoCs; ➂ The collaboration aims to leverage Cadence's advanced tools for the development of high-performance computing solutions.
➀ Cadence宣布开发并成功流片其首款基于Arm的系统芯片let；➁ 这标志着芯片let技术的重大进步；➂ 强调了Cadence通过其芯片let架构和框架推动行业领先解决方案的承诺。
1. Cadence has expanded its system IP portfolio with the introduction of the Cadence Janus Network-on-Chip (NoC). 2. The new NoC aims to optimize electronic system connectivity. 3. This expansion is expected to improve performance, power, and area (PPA) faster and with lower risk.
1. Cadence has announced a proprietary optical connectivity solution for PCIe 7.0. 2. The new solution promises data transfer speeds of up to 128 GT/s. 3. This development marks a significant advancement in high-speed data communication technologies.