➀ Mach42的发现平台利用机器学习创建一个代理模型，以实现更快的电路设计探索，而无需进行完整的SPICE模拟。
➁ 平台的目标是达到90%的准确率，允许快速迭代，同时保留在最终确认时进行完整准确性的选项。
➂ Mach42正在与Cadence合作开发Spectre，并计划开发Verilog-A模型，这可能会显著增强模拟-数字设计验证。
Recent #verification news in the semiconductor industry
➀ Siemens EDA在AI方面的深度，包括1400名AI专家和近4000项专利；
➁ 随着芯片复杂性的增加，行业预计到本世纪末将短缺27,000名专家设计师；
➂ Siemens利用三种类型的AI在验证领域：基于无监督学习的分析型AI、基于机器学习和统计分析的预测型AI，以及基于大型语言模型的生成/代理支持型AI。
➀ This article discusses the challenges of physical design verification for custom and analog/mixed-signal IC designs.
➁ It introduces Siemens' Calibre Pattern Matching tool for early-stage physical verification.
➂ The tool allows for interactive symmetry checking and early IP placement verification, reducing design time and improving quality.
➀ Synopsys has expanded its Hardware-Assisted Verification (HAV) portfolio to address the growing complexity of chip design.
➁ The new solutions aim to accelerate semiconductor design and system validation.
➂ Key products include the next-generation hardware engines ZeBu-200 and HAPS-200, offering significant performance improvements.
➀ Alpha Design AI is revolutionizing chip design and verification with ChipAgents, an AI tool that automates debugging and verification processes.
➁ The company is led by CEO and founder Dr. William Wang, who is also a professor at UC Santa Barbara.
➂ ChipAgents addresses industry challenges by integrating with existing EDA tools and reducing design cycle time.
➀ The complexities of modern IC designs with multiple clocks and asynchronous resets make reset logic more challenging than in early single-clock designs; ➁ Reset Domain Crossing (RDC) tools, like Questa RDC, perform static verification on reset logic to identify issues like glitches and metastability; ➂ Siemens' Questa RDC is effective in identifying structural and advanced reset tree issues, ensuring integrity before tapeout.
➀ Cadence推出一系列关于汽车设计趋势和挑战的网络研讨会；➁ 预计汽车半导体市场到2029年将以11%的复合年增长率增长；➂ 汽车OEM和一级供应商正朝着垂直整合的趋势发展。
➀ This blog discusses the use of objections in UVM code for synchronization. ➁ It provides examples and alternative approaches to using uvm_objection efficiently. ➂ The importance of not overusing objections to avoid slowing down simulations is emphasized.
➀ The evolving verification requirements of RISC-V as the architecture gains adoption; ➁ The role of standardization and infrastructure in supporting RISC-V’s growth; ➂ Challenges and opportunities in open-source functional verification for RISC-V.
➀ The RISC-V and open-source functional verification challenge highlights the differences in verification processes between RISC-V and ARM cores. ➁ The importance of selecting a reliable IP vendor and the impact of software support on verification is discussed. ➂ The role of RISC-V profiles in simplifying verification and enabling software compatibility is emphasized.
➀ The complexity of SoC designs continues to rise, making RDC verification challenging; ➁ Data analytics techniques can automate RDC verification, reducing manual analysis and improving efficiency; ➂ Case study shows a significant reduction in RDC violations through data-driven analysis.
1. The article discusses the relationship between System VIPs and PSS (Portable Stimulus Standard), highlighting the need for scalable, out-of-the-box solutions for system verification. 2. It explains that while PSS is a powerful tool for defining system-level tests, there is a growing demand for more canned system VIP solutions that simplify the testing process for non-experts. 3. The article also outlines the basic requirements and functionalities of System VIPs, emphasizing their role in generating traffic and monitoring system-level behaviors like cache coherence.