Recent #Analog Design news in the semiconductor industry

2 months ago

➀ Mach42的发现平台利用机器学习创建一个代理模型,以实现更快的电路设计探索,而无需进行完整的SPICE模拟。

➁ 平台的目标是达到90%的准确率,允许快速迭代,同时保留在最终确认时进行完整准确性的选项。

➂ Mach42正在与Cadence合作开发Spectre,并计划开发Verilog-A模型,这可能会显著增强模拟-数字设计验证。

Analog DesignCadenceEDAMach42SpectreVerilog-Amachine learningverification
11 months ago
1. Timing closure is critical for final chip design sign-off, especially with increasing interconnect resistance and capacitance parasitics. 2. Analog design lacks automation and heavily relies on handcrafted layouts and hand-estimated parasitics, leading to more post-layout issues. 3. The Cadence Quantus Insight Solution aims to accelerate expert designer insight and suggested fixes before long-cycle layout changes and re-simulation.
Analog DesignCadenceParasitic Extraction