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Today
- Design-Technology Co-Optimization (DTCO) Accelerates Market Readiness of Angstrom-Scale Process Technologies
➀ DTCO has transformed into a predictive strategy enabling co-development of process and design, exemplified by Synopsys' collaboration with Intel on 18A technology;
➁ Key advancements include RibbonFET alignment and PowerVia optimization, boosting design productivity and power efficiency in Intel’s 18A process;
➂ Synopsys’ PICO framework expands DTCO’s scope, ensuring full-stack optimization and enabling faster market readiness through pre-silicon validation.
- Optimizing an IR for Hardware Design. Innovation in Verification
➀ LLHD, a multi-level intermediate representation (IR) for hardware design, aims to bridge high-level languages and machine code, offering optimization opportunities across EDA workflows;
➀ Cadence’s Paul Cunningham highlights LLHD’s potential for academic research but notes challenges in commercial adoption due to maturity barriers;
➂ Raúl Camposano acknowledges LLHD’s alignment with open-source compiler innovations but questions its scalability compared to software ecosystems.
May 27
- WEBINAR: PCIe 7.0? Understanding Why Now Is the Time to Transition
➀ PCIe 7.0 achieves 128 GT/s bandwidth with PAM4 signaling and enhanced error correction, extending the innovations of PCIe 6.0;
➁ Key challenges involve managing multiple data movers and link layers, favoring bifurcation and dual-port interfaces over ultra-high clock speeds;
➂ PCIe 7.0 provides SoC designers flexibility for AI/HPC systems due to its cost-efficiency and low pin count compared to parallel buses.
- Andes Technology: Powering the Full Spectrum – from Embedded Control to AI and Beyond
➀ Andes Technology offers a comprehensive RISC-V processor portfolio spanning embedded control, AI/ML acceleration, and high-performance computing (HPC), with cores ranging from ultra-low-power D23 to Linux-capable multicore AX60;
➁ The AndesAIRE platform enables tailored AI inference engines through automated custom instructions and RISC-V vector extensions, with deployments in Meta's recommendation systems and EdgeQ's 5G chips;
➂ Automotive-grade ISO 26262 ASIL-D certified processors and cybersecurity applications with Cornami's FHE solutions demonstrate cross-industry adoption, cementing Andes' 30% RISC-V market leadership.
May 26
- From All-in-One IP to Cervell™: How Semidynamics Reimagined AI Compute with RISC-V
➀ Semidynamics' Cervell™ integrates CPU, vector, and tensor units into a unified RISC-V-based NPU, eliminating external CPU dependencies and performance bottlenecks;
➁ The architecture enables scalability from edge IoT devices to datacenters (up to 256 TOPS), with shared memory and customizable instructions through RISC-V's open ecosystem;
➂ Cervell challenges traditional NPUs by offering programmability, coherent task execution, and a simplified software stack for AI model optimization.
May 24
- Executive Interview with Mohan Iyer – Vice President and General Manager, Semiconductor Business Unit, Thermo Fisher Scientific
➀ Thermo Fisher Scientific focuses on enabling scientific breakthroughs through advanced solutions in metrology and defect analysis for semiconductor manufacturing;
➁ Key challenges addressed include R&D acceleration, yield management, and AI chip defect analysis with atomic-scale precision;
➂ Differentiation through automated workflows like Vulcan Automated Lab and specialized semiconductor division with global support networks.
- CEO Interview with Jason Lynch of Equal1
➀ Equal1 is pioneering silicon-based quantum computing with its Quantum System-on-Chip (QSoC) technology, integrating quantum and classical components into a single chip;
➁ The Bell-1 Quantum Server, their first commercial product, enables practical deployment in data centers through compact, energy-efficient designs;
➂ The company focuses on hybrid computing applications in pharmaceuticals, finance, and data center efficiency, addressing scalability and real-world integration challenges.
May 22
- Infinisim Enables a Path to Greater Profitability and a Competitive Edge
➀ Clock jitter significantly impacts chip performance, yield, and reliability, exacerbated by shrinking design margins in advanced process nodes;
➁ Infinisim's advanced clock verification platform enables precise analysis of jitter sources (e.g., PLL and PDN variations), surpassing traditional design margin approaches;
➂ By reducing conservative margins, Infinisim helps semiconductor companies maximize chip performance and profitability, avoiding market share loss through optimized clock strategies.
May 21
- Sébastien Dauvé with CEO of CEA-Leti
➀ Sébastien Dauvé, CEO of CEA-Leti, leads a leading European institute focused on microelectronics and nanotechnology, driving innovations in AI, quantum computing, and sustainable tech;
➁ CEA-Leti's 'lab-to-fab' model bridges R&D and industrial scaling, supported by partnerships under initiatives like the European Chips Act and the FAMES pilot line;
➂ The institute prioritizes cross-disciplinary collaboration and environmental impact, addressing challenges in healthcare, energy efficiency, and Europe's technological sovereignty.
- Turnkey Multi-Protocol Wireless for Everyone
➀ IoT devices require integrated wireless solutions to reduce costs and complexity;
➁ CEVA's Links200 platform provides a turnkey multi-protocol solution supporting Bluetooth 6.0, Auracast, and 802.15.4 standards;
➂ Combines low-power RF design with AI-enhanced features for wearables and smart homes.
May 20
- Alchip’s Technology and Global Talent Strategy Deliver Record Growth
➀ Alchip achieved record revenue of $1.62B in 2024 through leadership in 2nm/3nm ASIC design and chiplet-based packaging solutions;
➁ Strategic global talent redistribution focuses on Taiwan, Japan, and SEA, with Vietnam and Malaysia engineering teams doubling by 2025;
➂ Completed 18 TSMC CoWoS designs—the most among ASIC partners—enabling heterogeneous integration for AI/HPC systems.
- The Journey of Interface Protocols: Adoption and Validation of Interface Protocols – Part 2 of 2
➀ The interface protocol industry is consolidating due to compressed development timelines, with only large IP providers able to sustain investments in cutting-edge protocols like PCIe Gen6 and CXL.
➁ Security mechanisms like hardware root-of-trust and protocol-level encryption (e.g., PCIe IDE) have become fundamental to modern interface designs, requiring rigorous RTL validation.
➂ Hardware-assisted verification platforms (emulation/prototyping) now enable billions of test cycles for protocols like PCIe Gen5, reducing validation time by 50% through integrated solutions like SVK and IPK.
May 17
- CEO Interview with Sudhanshu Misra of ChEmpower Corporation
➀ ChEmpower Corporation leverages 25+ years of expertise to develop abrasive-free CMP pads, revolutionizing semiconductor planarization by eliminating defects and enabling eco-friendly manufacturing;
➁ Their technology addresses a $3B market with a $12B potential, targeting copper interconnects, advanced packaging, and sub-10nm nodes for AI chips and HBM applications;
➂ By integrating chemistry and materials innovation, ChEmpower uniquely competes against giants like DuPont while expanding into molybdenum and ruthenium solutions for next-gen chip materials.
- CEO Interview with Thar Casey of AmberSemi
➀ AmberSemi, a fabless semiconductor company, pioneers next-gen power management solutions with patented digital control and vertical power delivery, targeting 50% efficiency improvements in AI data centers;
➁ Its two core technologies—advanced power conversion and solid-state switching—eliminate cascade failures (3,000x faster protection) and reduce AI server power losses, saving $4B/year;
➂ The company collaborates with 50+ alpha/beta customers, with AC-DC conversion and protection product lines launching in 2024-2025 to address AI's escalating power demands.
May 15
- EDA AI agents will come in three waves and usher us into the next era of electronic design
➀ The EDA industry faces challenges from fragmented workflows and rising complexity in semiconductor/PCB systems, requiring AI-driven automation;
➁ Three waves of AI integration are identified: task-specific agents, autonomous agentic AI, and collective multi-agent systems;
➂ These AI advancements will transform design workflows, boost productivity, and democratize expertise across organizations.
- Webinar – Achieving Seamless 1.6 Tbps Interoperability with Samtec and Synopsys
➀ AI-driven system design demands push for 1.6T Ethernet and 224G SerDes technology to address exponential data bandwidth needs;
➁ Synopsys and Samtec detailed interoperability challenges, including channel modeling and co-packaged interconnect solutions for 224G/448G PAM4 signaling;
➂ Collaborative ecosystem approach emphasized for achieving seamless 1.6 Tbps scalability in AI/ML infrastructure.
May 14
- Safeguard power domain compatibility by finding missing level shifters
➀ Level shifters are crucial for voltage compatibility in mixed-signal IC designs, but missing them is common due to design complexity and human factors;
➁ Missing level shifters can cause signal errors, device damage, and power inefficiency, especially in multi-voltage domain designs;
➂ Siemens EDA's Insight Analyzer tool enables early detection of missing level shifters through advanced voltage analysis without requiring simulation.
- A Timely Update on Secure-IC
➀ Cadence announced plans to acquire Secure-IC in 2025, highlighting its role in providing end-to-end security solutions across automotive, defense, and IoT markets;
➁ Secure-IC's Securyzr platform offers comprehensive security services, including post-quantum cryptography, AI-driven threat detection, and cloud-based fleet management for device lifecycle security;
➂ The company supports compliance with global standards (e.g., FIPS, Common Criteria) and provides specialized tools for side-channel attack analysis, positioning itself as a critical partner for security-sensitive industries.
May 13
- The Journey of Interface Protocols: The Evolution of Interface Protocols – Part 1 of 2
➀ The rise of AI has intensified demands for hardware performance, driving rapid evolution of interface protocols like PCIe and Ethernet to support high bandwidth and low latency;
➁ New protocols such as UCIe and Ultra Accelerator Link are emerging to address AI-specific needs, enabling multi-die architectures and cache coherency across CPUs/GPUs;
➂ Protocol complexity has surged, with PCIe Gen 7 specifications exceeding 2,000 pages and Ultra Ethernet targeting 224 GB/s speeds to compete with NVIDIA's NVLink.
- Leveraging Common Weakness Enumeration (CWEs) for Enhanced RISC-V CPU Security
➀ RISC-V的开放性和可定制性带来了硬件安全风险，需在芯片设计早期进行威胁检测；
➁ MITRE CWE框架新增108个硬件相关漏洞分类，并针对瞬态执行攻击（如Spectre和Meltdown）引入三类微架构缺陷枚举；
➂ Cycuity的Radix工具通过架构无关的信息流分析，支持RISC-V芯片设计中的安全验证与漏洞预防。
May 12
- Metal fill extraction: Breaking the speed-accuracy tradeoff
➀ Metal fill is critical for semiconductor manufacturing to ensure layer uniformity and thermal management, but introduces parasitic capacitances affecting circuit performance;
➁ Traditional extraction methods struggle with accuracy-efficiency tradeoffs, causing timing violations and delayed iterations;
➂ Siemens' adaptive metal fill extraction technique achieves 4x faster runtime with minimal accuracy loss through context-aware parasitic modeling.
- How Arteris is Revolutionizing SoC Design with Smart NoC IP
➀ Arteris demonstrated Smart NoC technology at IP-SoC Days, addressing the growing complexity of SoC design through automation and AI-driven optimization.
➁ FlexGen, its non-coherent NoC IP, accelerates chip design by up to 10x, reduces wire length by 30%, and supports diverse processor architectures (Arm, RISC-V, x86).
➂ With over 3.7B SoCs shipped and 90%+ customer retention, Arteris technologies are used by 9 of the top 10 semiconductor companies.
May 11
- CEO Interview with Ido Bukspan of Pilops
➀ Pliops accelerates GenAI infrastructure performance through its XDP LightningAI, improving data access by 50x while reducing computational load;
➁ The company focuses on GPU-centric solutions to enhance AI/ML applications' efficiency, cutting power consumption and carbon footprint;
➂ Pliops addresses critical challenges in data center power constraints and AI infrastructure margins through innovative memory tiering and resource optimization.
- CEO Interview with Roger Cummings of PEAK:AIO
➀ PEAK:AIO develops software-defined storage systems converting commodity hardware into AI-optimized infrastructure, addressing data bottlenecks in enterprises.
➁ The company targets healthcare, life sciences, and government sectors, supporting high-impact projects like UK's NHS and LANL research with 6X performance improvements.
➂ With CXL/NVMe integrations and dynamic tiered storage, PEAK:AIO differentiates from legacy vendors through energy efficiency, simplicity, and workload-specific architectures.
May 8
- Analog Bits Steals the Show with Working IP on TSMC 3nm and 2nm and a New Design Strategy
➀ Analog Bits demonstrated six precision analog IP blocks on TSMC's cutting-edge 2nm process at the TSMC Technology Symposium, including PLLs with 5-2000MHz frequency range and sub-0.8ps jitter performance.
➁ The company showcased its Intelligent Power Architecture for multi-die systems, integrating PVT sensors, droop detectors, and LDO regulators to address power management challenges in advanced packaging designs.
➂ Proven pinless IP technology enabling core-voltage-only operation was highlighted as crucial for sub-3nm nodes, with production validation already completed on N5 and N3 processes.
- RISC-V Virtualization and the Complexity of MMUs
➀ RISC-V is expanding from microcontroller to application processors and data center servers, requiring robust virtualization support through MMU standards;
➁ The RISC-V MMU standard introduces complexity due to its recent finalization, ISA extensions, and generalized design, challenging verification teams;
➂ Breker's SystemVIP tool addresses MMU verification gaps, offering testplan frameworks despite ongoing refinements and debates over compliance.
May 7
- Beyond the Memory Wall: Unleashing Bandwidth and Crushing Latency
➀ VSORA's TCM architecture minimizes data movement and reduces latency through register-like memory access;
➁ Reconfigurable compute tiles enable dynamic precision switching and high utilization for AI workloads;
➂ An intelligent compiler automates LLM deployment, bypassing GPU memory bottlenecks for edge and data-center applications
- Intel’s Foundry Transformation: Technology, Culture, and Collaboration
➀ Intel is undergoing a cultural shift from product-centric to customer-focused foundry operations, partnering with UMC to target the 12nm process node for a $20B market by 2028;
➁ Parallel development at UMC's Taiwan facility and Intel's Arizona site supports geo-diversified manufacturing, with 12nm offering 28% better performance and 47% lower power than previous nodes;
➂ The collaboration accelerates Intel's cultural transformation by leveraging UMC's foundry expertise in customer service and operational efficiency.
- Speculative Execution: Rethinking the Approach to CPU Scheduling
➀ Speculative execution, pioneered by IBM 360, improves CPU performance through branch prediction but introduces complexity and security risks;
➁ Modern implementations consume 25-35% of silicon area and 20% power, with vulnerabilities like Spectre requiring performance-sacrificing patches;
➂ Dr. Thang Tran proposes predictive execution models to eliminate speculative overheads, offering energy-efficient and secure alternatives for AI and cloud computing.
April 1
- A Synopsys Webinar Detailing IP Requirements for Advanced AI Chips
➀ The webinar discusses the impact of generative AI on technology evolution and the rise in compute power demand.
➁ It covers the trends in larger compute chips, multi-die systems, advanced packaging, and memory architectures.
➂ Key technologies like die-to-die communication, custom HBMs, and 3D stacking are explored in detail.