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September 1
- Beyond Traditional OOO: A Time-Based, Slice-Based Approach to High-Performance RISC-V CPUs
➀ High-performance CPU design is transitioning from traditional Out-of-Order (OOO) architectures to Time-Based OOO, leveraging RISC-V's open ecosystem to improve power efficiency and scalability.
➁ Condor Computing's Cuzco processor uses a slice-based microarchitecture and predictive scheduling via a Time Resource Matrix, enabling flexible configurations for datacenter, mobile, and automotive applications.
➂ Key advantages include superior performance-per-watt, simplified verification, and ISA extensibility, positioning RISC-V as a competitive alternative to legacy architectures like x86 and ARM.
- Orchestrating IC verification: Harmonize complexity for faster time-to-market
➀ Modern IC verification complexity demands orchestrated workflow systems akin to conducting an orchestra, enabling unified management of tasks across tools and teams;
➁ Fragmented verification processes lead to inefficiencies such as manual errors and resource bottlenecks, while orchestration systems provide automation, intelligent resource allocation, and centralized monitoring;
➂ Siemens' Calibre MJS exemplifies this approach, reducing runtime by 30%-50% and improving design iteration efficiency through features like single-layout streaming and license optimization.
August 31
- Basilisk at Hot Chips 2025 Presented Ominous Challenge to IP/EDA Status Quo
➀ Basilisk is a groundbreaking RISC-V SoC developed with fully open-source EDA tools, demonstrating Linux capability on industrial-grade silicon via mature 130nm BiCMOS process；
➁ The project challenges traditional IP/EDA business models, highlighting U.S. incumbents' innovation stagnation versus rapid progress in Europe and China pursuing sovereign chip ecosystems；
➂ Open-source tools like Yosys and OpenROAD achieved silicon success with 64-102MHz operation, GPU-like voltage scalability, and energy efficiency optimization, enabling next-gen 22nm FD-SOI designs
- CEO Interview with Nir Minerbi of Classiq
➀ Classiq is a quantum software startup specializing in automated quantum algorithm design, allowing users to focus on functional requirements rather than manual gate-level coding;
➁ The company targets enterprise applications in finance, pharmaceuticals, automotive, and aerospace, addressing challenges like portfolio optimization and molecular simulations;
➂ Classiq differentiates through its high-level modeling language (Qmod) and patented synthesis engine, achieving up to 97% quantum circuit compression while supporting multi-platform deployments.
August 29
- GlobalFoundries 2025 Update GTS25
➀ GlobalFoundries (GF) has solidified its role as a leading contract semiconductor manufacturer, focusing on automotive, IoT, and autonomous systems with mature technologies like FD-SOI and FinFET.
➁ GF reported strong Q2 2025 revenue of $1.688 billion, driven by strategic partnerships and acquisitions, including MIPS Technologies to expand RISC-V IP for AI applications.
➂ Despite market volatility and geopolitical risks, GF emphasizes sustainability and regional strategies (e.g., 'China-for-China') to secure its position as the third-largest pure-play foundry globally.
August 28
- Perforce and Siemens at #62DAC
➀ Siemens and Perforce discussed their collaboration on integrating IP lifecycle management (IPLM) with semiconductor tools, emphasizing software-defined products and system-level verification;
➁ The digital twin approach and metadata interoperability across EDA tools enable traceability from requirements to verification, critical for automotive and safety-critical systems;
➂ AI-powered tools and data lakes are leveraged to optimize verification efficiency and manage design decisions across hardware-software co-development.
- Synopsys Enables AI Advances with UALink
➀ Hyperscale data centers face scaling and memory access challenges for large AI models requiring trillions of parameters;
➁ Synopsys leads the UALink consortium, an open standard for AI accelerator communication, co-developed with over 100 companies including AMD, Meta, and Microsoft;
➂ Synopsys' UALink and Ultra Ethernet IP solutions enable clusters of 1,024 accelerators and 1 million nodes, addressing bandwidth, latency, and memory sharing for AI infrastructure.
- Perforce and Siemens: A Strategic Partnership for Digital Threads in EDA
➀ Siemens and Perforce integrate digital twins with version control to streamline semiconductor design workflows;
➁ The partnership establishes traceable digital threads across chip design lifecycle using Siemens' virtual simulation and Perforce's data management;
➂ This collaboration addresses complex challenges in AI-driven chip architectures while targeting $1 trillion semiconductor market growth by 2030.
- AI’s Transformative Role in Semiconductor Design and Sustainability
➀ AI accelerates semiconductor R&D through automated analog/digital design flows, reducing analog design time from months to days;
➁ STMicroelectronics employs AI for eco-design, optimizing energy use in chips and enabling green technologies like smart grids and solar farms;
➂ Federated learning proposed for academic prototyping, allowing collaborative AI model training while protecting sensitive chip design/IP data.
August 27
- Cocotb for Verification. Innovation in Verification
➀ The paper compares UVM and Python-based Cocotb for AES hardware verification, showing Cocotb's 89.55% code coverage vs. UVM's 87.49%, but raises questions about UVM's low functional coverage (47/64 cases) without clear explanations;
➁ UVM demonstrated faster simulation time (1000ns vs. Cocotb's 10,000.5ns), though experts note Cocotb's flexibility with Python libraries and simpler synchronization offer workflow advantages for early RTL development;
➂ Cadence's Paul Cunningham highlights UVM's commercial EDA tool integration and constraint solver optimizations, while Raúl Camposano observes Cocotb's growing relevance in AI-driven verification ecosystems despite the paper's methodological limitations.
August 25
- Intel’s Pearl Harbor Moment
➀ Intel's monopolistic mindset and dismissal of fabless models led to complacency, allowing TSMC and competitors to surpass its manufacturing dominance;
➁ Critical failures in 10nm/7nm process transitions, product delays, and strategic exits from mobile/GPU markets eroded Intel’s technological leadership;
➂ Despite recent government backing and leadership changes, Intel must regain trust through innovation and collaboration with fabless partners.
- A Big Step Forward to Limit AI Power Demand
➀ NVIDIA and Cadence collaborate to address critical pre-silicon power estimation challenges for AI chips through advanced emulation and DPA technology;
➁ Traditional power estimation methods face scalability and accuracy limitations with AI's billion-gate designs and complex workloads, necessitating gate-level analysis with full benchmark coverage;
➂ Cadence's new DPA App on Palladium Z3 achieves 97% post-silicon power correlation by executing billion-cycle emulations in hours, enabling precise optimization for energy-efficient AI hardware design.
August 24
- Free and Open Chip Design Tools: Opportunities, Challenges, and Outlook
➀ Semiconductor design faces high barriers due to proprietary EDA tool monopolies;
➁ Open-source EDA tools and PDKs are reducing costs and enabling innovation in education and commercial projects;
➂ Challenges persist in advanced node support and industry adoption despite security and accessibility advantages.
- Chiplets: providing commercially valuable patent protection for modular products
➀ Chiplet-based SoCs offer increased yield, design flexibility, and simplified assembly compared to traditional monolithic SoCs；
➁ UK patent enforcement becomes complex for chiplet-based designs, as individual chiplets may not directly infringe all patent claims；
➂ Drafting patents to cover individual chiplets rather than entire systems is advised for stronger IP protection.
August 22
- WEBINAR: Functional ECO Solution for Mixed-Signal ASIC Design
➀ The webinar discusses challenges in functional ECO (Engineering Change Order) for mixed-signal ASIC designs across smartphones, automotive, and IoT applications;
➁ Easy-Logic Technology presents specialized algorithms and methodologies to optimize ECO processes impacted by analog-digital integration and tight timelines;
➂ Their decade-long expertise addresses complex scenarios like iterative ECO cycles, RTL/netlist co-modification, and post-test chip revisions.
August 21
- Taming Concurrency: A New Era of Debugging Multithreaded Code
➀ Modern computing systems face significant challenges in debugging concurrent code due to non-deterministic behaviors like race conditions and deadlocks;
➁ Time Travel Debugging (TTD) revolutionizes debugging by enabling full execution trace analysis, deterministic reproduction of issues, and integration with thread fuzzing for proactive defect discovery;
➂ Technologies like Undo’s multi-process correlation and shared memory logging are transforming debugging workflows, adopted by major tech firms to enhance reliability and efficiency.
- Perforce Webinar: Can You Trust GenAI for Your Next Chip Design?
➀ Perforce will host a webinar on September 10 to discuss the risks and trustworthiness of using GenAI in chip design, featuring expert Vishal Moondhra;
➁ Key concerns include data liability, lack of training traceability, high error costs, and data quality issues in mixing external/internal IP;
➂ The webinar will explore solutions for managing AI model provenance and implementing traceable design workflows using Perforce IPLM tools.
August 20
- Weebit Nano Moves into the Mainstream with Customer Adoption
➀ Weebit Nano's ReRAM technology achieves commercial milestones through partnerships with onsemi and DB HiTek;
➁ ReRAM demonstrates advantages over flash memory in power consumption, speed, and high-temperature applications (e.g., automotive/industrial);
➂ First U.S. design license signed for security applications, with multiple licensing deals anticipated in 2024.
- A Principled AI Path to Spec-Driven Verification
➀ Breker tackles the challenges of automating verification by addressing rapid spec changes and ambiguous requirements through AI-driven approaches;
➁ Their strategy combines traditional NLP-based methods for deterministic test synthesis with future LLM partnerships to enhance scalability;
➂ The approach emphasizes a 'principled' foundation to ensure reliability, leveraging decades of verification expertise in RISC-V, Arm, and SoC validation.
August 19
- Exploring the Latest Innovations in MIPI D-PHY and MIPI C-PHY
➀ MIPI D-PHY and C-PHY standards have evolved to support up to 11 Gbps and 24.84 Gbps per-lane throughput, respectively, through advanced signal integrity techniques like DFE and 18-Wirestate encoding;
➁ Innovations such as Alternate Low Power (ALP) mode in D-PHY and enhanced voltage slicing in C-PHY improve energy efficiency and reliability for automotive, XR, and industrial applications;
➂ MIPI D-PHY v3.5 introduces Embedded Clock Mode (ECM), increasing throughput by 25% and reducing EMI, while C-PHY v3.0 achieves faster lane turnaround and higher encoding efficiency.
- 448G: Ready or not, here it comes!
➀ The development of 448G SerDes is critical for scaling Ethernet beyond 1.6T, supporting AI/data center infrastructures through advanced modulation schemes like PAM4/PAM6.
➁ Industry standards bodies (OIF, IEEE, SNIA) are collaborating on specifications, while Synopsys accelerates PHY development via channel topology analysis and DSP architecture modeling.
➂ Key technical challenges include managing symbol transition complexity and balancing power/performance trade-offs in 448G SerDes implementations.
August 18
- Should the US Government Invest in Intel?
➀ Intel's historical lack of competition and recent leadership changes under CEO Lip-Bu Tan are central to its revitalization efforts;
➁ Political tensions, including accusations from Senator Tom Cotton and reactions from Donald Trump, highlight challenges in U.S.-China relations and Intel's strategic position;
➂ The debate centers on whether U.S. government investment should prioritize maintaining Intel as a leading-edge semiconductor manufacturer amidst geopolitical pressures.
- PDF Solutions and the Value of Fearless Creativity
➀ PDF Solutions has over 30 years of experience in semiconductor manufacturing and yield optimization, evolving into an AI-driven data platform addressing 3D innovation, supply chain complexity, and operational efficiency;
➁ Its cloud-based infrastructure manages 2.5PB of manufacturing data, facilitating collaboration across design, production, and global supply chains through tools like contactless eProbe wafer testing;
➂ The company emphasizes fearless creativity in solving industry challenges, partnering with hyperscalers and integrating open platforms for ecosystem-wide innovation.
August 17
- AMAT China Collapse and TSMC Timing Trimming
➀ Applied Materials (AMAT) reported a significant Q4 revenue drop of $1B, driven by a $500M decline in China (due to export restrictions and market saturation) and a $500M slowdown in advanced logic/foundry projects, with TSMC delaying fab expansions;
➁ The semiconductor equipment cycle has turned negative, potentially ending China's prolonged capex growth and increasing TSMC's pricing power over suppliers;
➂ Memory markets remain viable only in HBM segments, while equipment stocks face reality checks with AMAT shares plunging 14% amid lowered investor confidence in sector resilience.
- CEO Interview with Russ Garcia with Menlo Micro
➀ Menlo Micro leverages MEMS-based Ideal Switch technology to overcome limitations of traditional relays and solid-state switches in RF and power systems;
➁ Key applications include semiconductor testing for AI GPUs (accelerating PCIe Gen6/7 testing), aerospace beamforming systems, and smart power grids with 1000VDC/125A modules;
➂ Proprietary metallurgy enables 10x size reduction, billion-cycle durability, and operation from -273°C to +150°C, addressing thermal and signal integrity challenges.
August 14
- Semiconductors Still Strong
➀ Global semiconductor market surged to $180 billion in 2Q 2025, up 19.6% YoY, led by NVIDIA's $45B revenue and robust memory sector growth;
➁ Memory giants SK Hynix (26% QoQ) and Micron (16%) drove gains, while tariffs and AI demand shaped market dynamics;
➂ 2025 full-year growth forecasts revised to 13-16%, with uncertainties around U.S.-China trade tensions and smartphone market declines.
- Moving Beyond RTL at #62DAC
➀ Rise Design Automation showcased a next-gen HLS methodology at DAC, blending SystemVerilog/C++/SystemC with AI-driven tools to boost design efficiency;
➁ Their platform integrates LLM-based AI advisors for code generation and verification acceleration, achieving 100X-1,000X faster verification through high-level abstraction;
➂ The solution enables multi-language design exploration, automated testbench creation, and interoperability with EDA tools like VCS and Open ROAD, targeting area/power/performance optimization.
April 1
- A Synopsys Webinar Detailing IP Requirements for Advanced AI Chips
➀ The webinar discusses the impact of generative AI on technology evolution and the rise in compute power demand.
➁ It covers the trends in larger compute chips, multi-die systems, advanced packaging, and memory architectures.
➂ Key technologies like die-to-die communication, custom HBMs, and 3D stacking are explored in detail.
- CEO Interview with Matthew Stephens of Impact Nano
➀ Matthew Stephens of Impact Nano has over 20 years of experience in advanced materials commercialization.
➁ Impact Nano is a tier 2 supplier specializing in advanced materials for semiconductor manufacturing.
➂ The company addresses challenges in materials innovation, scale-up, and manufacturing sustainability.
March 31
- An Important Advance in Analog Verification
➀ Mach42的发现平台利用机器学习创建一个代理模型，以实现更快的电路设计探索，而无需进行完整的SPICE模拟。
➁ 平台的目标是达到90%的准确率，允许快速迭代，同时保留在最终确认时进行完整准确性的选项。
➂ Mach42正在与Cadence合作开发Spectre，并计划开发Verilog-A模型，这可能会显著增强模拟-数字设计验证。