➀ High-performance CPU design is transitioning from traditional Out-of-Order (OOO) architectures to Time-Based OOO, leveraging RISC-V's open ecosystem to improve power efficiency and scalability.

➁ Condor Computing's Cuzco processor uses a slice-based microarchitecture and predictive scheduling via a Time Resource Matrix, enabling flexible configurations for datacenter, mobile, and automotive applications.

➂ Key advantages include superior performance-per-watt, simplified verification, and ISA extensibility, positioning RISC-V as a competitive alternative to legacy architectures like x86 and ARM.

➀ Basilisk is a groundbreaking RISC-V SoC developed with fully open-source EDA tools, demonstrating Linux capability on industrial-grade silicon via mature 130nm BiCMOS process；

➁ The project challenges traditional IP/EDA business models, highlighting U.S. incumbents' innovation stagnation versus rapid progress in Europe and China pursuing sovereign chip ecosystems；

➂ Open-source tools like Yosys and OpenROAD achieved silicon success with 64-102MHz operation, GPU-like voltage scalability, and energy efficiency optimization, enabling next-gen 22nm FD-SOI designs

➀ GlobalFoundries (GF) has solidified its role as a leading contract semiconductor manufacturer, focusing on automotive, IoT, and autonomous systems with mature technologies like FD-SOI and FinFET.

➁ GF reported strong Q2 2025 revenue of $1.688 billion, driven by strategic partnerships and acquisitions, including MIPS Technologies to expand RISC-V IP for AI applications.

➂ Despite market volatility and geopolitical risks, GF emphasizes sustainability and regional strategies (e.g., 'China-for-China') to secure its position as the third-largest pure-play foundry globally.

➀ Codasip launched Codasip Prime, a pre-silicon platform integrating CHERI technology to enhance memory safety and security in RISC-V-based systems;

➁ The platform includes FPGA hardware, a software development kit, and CHERI-specific IP to enable secure software development and compliance with regulations like the EU Cyber Resilience Act;

➂ CHERI addresses 87% of memory-related cyberattacks, offering cost-effective protection without requiring full software rewrites, with Codasip collaborating with the CHERI Alliance to standardize RISC-V extensions.

➀ Over 250 billion Arm chips have been shipped since 1985, powering devices from handhelds to datacenters;

➁ ARM1's 3μm/6,000-gate RISC design pioneered energy efficiency through resource constraints, evolving to 3nm/100M+ gates today;

➂ While maintaining dominance in mobile and expanding to AI/datacenters, Arm faces challenges from RISC-V and China's semiconductor ambitions.

Chinese researchers have built a 32-bit RISC-V processor using molybdenum disulfide (MoS2) on a sapphire substrate. The processor, RV32-WUJI, has 6000 transistors and operates at KHz speeds, executing the full RISC-V 32-bit instruction set. The researchers used machine learning to optimize the wiring and materials for the transistors. The overall yield was over 99.9 percent, with a chip-level yield of 99.8 percent.

➀ There has been a significant shift towards RISC-V architectures in SoC design;

➁ This article highlights the impact of this shift on the semiconductor industry;

➂ It discusses the role of RISC-V in fostering innovation and flexibility in technology development.

➀ A roundup of the latest electronics news from Embedded World 2024, covering automotive, military, telecoms, industrial, and consumer electronics sectors.

➁ Infineon is launching a RISC-V starter kit for automotive microcontrollers.

➂ NXP reveals MCX MCUs with Matter, Thread, Zigbee, and Bluetooth LE.

➀ Bolt Graphics has introduced its Zeus GPU platform, designed for gaming, rendering, and supercomputer simulations.

➁ The company claims that its Zeus GPU can outperform Nvidia's GeForce RTX 5090 by around 10 times in path tracing workloads.

➂ However, Zeus is limited to path tracing and FP64 compute workloads due to its lack of support for traditional rendering techniques.

➀ Infineon推出面向未来几年发布的汽车微控制器系列的RISC-V入门套件；

➁ Infineon汽车总裁Peter Schiefer表示，在软件定义的汽车中，RISC-V是实现标准化和生态系统兼容性的关键；

➂ 该套件将由Synopsys提供，旨在推动虚拟MCU原型的开发，以促进软件开发，并最终实现真实硅片的制造。

➀ China plans to release guidelines encouraging the national use of RISC-V-based chips, according to a Reuters report.

➁ The RISC-V architecture is attractive due to its openness, allowing anyone to freely obtain, learn, modify, and extend it.

➂ RISC-V has been embraced by global companies like Alibaba, Qualcomm, and NVIDIA, contributing to its rapid development.

➀ The Chinese government is shifting its focus from x86 and Arm CPUs to promote RISC-V chips, aiming to reduce reliance on foreign technologies.

➁ The new policy is expected to be announced soon, marking the first official government push for RISC-V adoption in China.

➂ Chinese companies like Alibaba and Nuclei System Technology are investing in RISC-V, and the technology is gaining traction in the country.

➀ RISC-V has transformed from an emerging force to a mainstream one after more than a decade of development;

➁ More and more companies are entering the RISC-V field and achieving remarkable results, with Qualcomm shipping 650 million RISC-V cores by the end of 2023 and ARM producing about 3 billion chips based on RISC-V cores;

➂ Alibaba's DAMO Academy Xuan Tie team is fully committed to RISC-V, revealing breakthroughs in server-grade CPU and showcasing the full picture of the high-performance ecosystem.

➀ RISC-V is emerging as the native computing architecture for AI.

➁ DeepSeek's success has sparked innovation in computing architecture.

➂ RISC-V, with its open-source nature, is well-suited AI applications.

➃ The flexibility and scalability of RISC-V make it ideal for AI computing.

➄ The first server-grade CPU based on RISC-V, C930, is set for delivery.

➅ Alibaba's XuanTie leads the international open-source community in RISC-V development.

➆ RISC-V is poised to become the dominant architecture in AI accelerators by 2030.

➀ Andes Technology and proteanTecs have formed a strategic partnership;

➁ The collaboration allows joint customers to integrate proteanTecs' on-chip monitoring IP into Andes' RISC-V cores;

➂ The partnership aims to enhance performance and reliability monitoring for RISC-V cores.

➀ Breker Verification Systems宣布其RISC-V SystemVIP库组件和测试套件合成产品组合已部署在超过15个商业RISC-V半导体设计项目中；

➁ 其RISC-V产品也被用于多个大型学术项目；

➂ 这些项目涉及大型、复杂的应用处理器。

➀ A group of former Intel engineers and executives have raised $21.5 million in seed funding for their RISC-V startup, AheadComputing.

➁ The company, based in Portland, Oregon, is using RISC-V to tackle the processing demands of AI.

➂ Investors include notable figures such as Jim Keller, CEO of RISC-V developer Tenstorrent, and Eclipse Ventures.

➀ Nandni Jamnadas is a UKESF Scholar and a student at Royal Holloway, University of London, also working as a Software Tool Chain Engineer at Embecosm.

➁ She is a member of the Embecosm GNU compiler team and leads the CORE-V GNU tool chain project.

➂ Her achievements include contributing to GNU, creating tailored tool chains for customers, and implementing new features in the CORE-V tool chain.