➀ NVIDIA and Cadence collaborate to address critical pre-silicon power estimation challenges for AI chips through advanced emulation and DPA technology;
➁ Traditional power estimation methods face scalability and accuracy limitations with AI's billion-gate designs and complex workloads, necessitating gate-level analysis with full benchmark coverage;
➂ Cadence's new DPA App on Palladium Z3 achieves 97% post-silicon power correlation by executing billion-cycle emulations in hours, enabling precise optimization for energy-efficient AI hardware design.