➀ Intel's monopolistic mindset and dismissal of fabless models led to complacency, allowing TSMC and competitors to surpass its manufacturing dominance;

➁ Critical failures in 10nm/7nm process transitions, product delays, and strategic exits from mobile/GPU markets eroded Intel’s technological leadership;

➂ Despite recent government backing and leadership changes, Intel must regain trust through innovation and collaboration with fabless partners.

➀ TSMC denies delaying Japan/Germany fabs, stresses U.S. expansion won't disrupt other regions;

➀ Arizona Fab 21 phase 2 accelerated for 2027 3nm AI chip production;

➂ Japan/Germany delays attributed to infrastructure readiness, not resource allocation.

➀ Samsung delays equipping its Texas fab to 2026 due to lack of customers for its 2nm process;

➁ TSMC dominates 2nm production with Apple, MediaTek, and AMD as major clients, planning significant capacity expansion;

➂ Intel faces challenges with its 18A process amid high TSMC wafer costs impacting industry competition.

➀ Intel may halt marketing its 18A process to foundry customers, focusing instead on 14A, which could leverage high-NA EUV advantages to compete with TSMC;

➁ TSMC dominates the 2nm foundry market with high yields and significant planned capacity (50k wpm by 2025, 120-130k wpm by 2026), securing major clients like Apple and AMD;

➂ Existing 18A contracts with Microsoft and Amazon will continue, though Intel’s strategic shift aims to prioritize 14A for future competitiveness.

➀ Yole Group predicts China will dominate global semiconductor foundry capacity by 2030, reaching 30% share despite US sanctions;

➁ China's wafer production surged to 8.85M/month in 2024, with 18 new fabs like Huahong Semiconductor driving growth;

➂ The US relies heavily on imports (57% demand vs. 10% production), but ongoing TSMC/Intel projects and tech export controls add uncertainty to China's advanced chip ambitions.

➀ Ex-Intel CEO Pat Gelsinger advises Japan's Rapidus to develop unique differentiating technologies beyond production efficiency to compete with TSMC.

➁ Rapidus plans to integrate wafer fabrication and advanced packaging at the same facility for faster cycles, though full automation will not be available immediately from 2027.

➂ The company aims to begin 2nm test production with GAA transistors and establish a chiplets R&D center, utilizing ASML EUV lithography tools for future HBM and 3D packaging.

➀ Counterpoint Research's analysis defines Foundry 2.0 as encompassing packaging and mask-making alongside wafer fabrication, with TSMC leading at 35% market share and Intel ranking second at 6.5%;

➁ The expanded definition may mitigate monopoly concerns for TSMC, whose traditional wafer fabbing dominance reaches nearly 70%;

➂ The Foundry 2.0 market reached $72 billion in Q1 2025, with Intel gaining 0.6% quarterly market share but declining 0.3% year-over-year.