Recent #Layout Verification news in the semiconductor industry

3 months ago

➀ This article discusses the challenges of physical design verification for custom and analog/mixed-signal IC designs.

➁ It introduces Siemens' Calibre Pattern Matching tool for early-stage physical verification.

➂ The tool allows for interactive symmetry checking and early IP placement verification, reducing design time and improving quality.

Calibre Pattern MatchingEDAEarly VerificationIC DesignIP ReuseLayout VerificationPhysical DesignSiemensSymmetry Checkingverification