➀ ECO (Engineering Change Order) is crucial for post-layout modifications in mixed-signal ASIC designs, addressing challenges from analog-digital interactions;

➁ Richard Chang's webinar explores three key drivers of ECO requirements and demonstrates Easylogic's automated solutions to reduce turnaround time and design complexity;

➂ The session provides practical insights on RTL-based tracing and seamless integration for tapeout success.

➀ The webinar discusses challenges in functional ECO (Engineering Change Order) for mixed-signal ASIC designs across smartphones, automotive, and IoT applications;

➁ Easy-Logic Technology presents specialized algorithms and methodologies to optimize ECO processes impacted by analog-digital integration and tight timelines;

➂ Their decade-long expertise addresses complex scenarios like iterative ECO cycles, RTL/netlist co-modification, and post-test chip revisions.