Recent #2nm news in the semiconductor industry

about 1 year ago
➀ Google is rumored to switch to TSMC's N3E process for Tensor G5; ➁ The report also clarifies that Google has chosen not to use 2nm technology for Tensor G6; ➂ The move could impact the competition in the AI and smartphone chip markets.
2nm3D IC3nmAIAI PCAI chipAMDASUSArmCPUChipletDRAMDellEDAGDDRGPUGaNHBMHPCInfineonLinuxNPUNVIDIAPCIePrivacyRaspberry PiSEMICONDUCTORSK hynixSSDSwitchTITSMCautomotivecoolingcybersecuritygamingiOSlaptopmemorymicrochipmonitorsoftware
about 1 year ago
➀ Raspberry Pi introduces the new AI HAT+ with two variants, 13 and 26 TOPS; ➁ The HAT+ is based on Hailo-8 neural network inference accelerators; ➂ The 26 TOPS variant is designed for larger networks and can run multiple networks simultaneously.
2nm3D ICAIAI ChipAMDArmAsusCoolingDellEDAGDDRGaNHPCInfineonLaptopLinuxMicrochipPCIePrivacyRaspberry PiSoftwareSwitchTIautomotivecybersecuritygaminghardwareiosmemorymonitorsemiconductor
about 1 year ago

➀ TSMC reports a strong demand for 2nm nodes over 3nm, with A16 attracting AI server clients.

➁ TSMC's 3nm shipments accounted for 20% of total wafer revenue in Q3 2024.

➃ TSMC's 2nm is expected to enter volume production in 2025.

➄ TSMC plans to expand its 2nm capacity to meet strong demand.

➅ TSMC's A16 process is highly attractive for AI server applications.

2nm3nmA16AI ServerHigh-Performance ComputingTSMC
about 1 year ago
➀ Imec spin-off Brailsports is developing a platform for optimizing athlete training volumes and schedules based on data analysis; ➁ The platform uses AI models to estimate individual athlete fitness and fatigue, improving performance and reducing injury risk; ➂ The platform is currently operational at cycling team Lotto Dstny, with positive results.
2nm3nmAIAI ChipAI PCAMDArmAsusCoolingDellGDDRGaNHBMHPCInfineonLaptopLinuxMicrochipNPUNVIDIAPCIePrivacyRaspberry PiSK HynixSoftwareSwitchTIautomotivecybersecuritygamingiosmemorymonitorsemiconductor
about 1 year ago
➀ Arm is exploring the feasibility of running LLMs on mobile devices; ➁ Arm's optimization techniques for LLMs on mobile; ➂ The importance of practical use cases for LLMs in mobile devices
2nm3D IC3nmAIAI PCAI chipAMDASUSArmCPUChipletDRAMDellEDAEMIBEUVGDDRGPUGaNHBMHPCInfineonLinuxMobileNPUNVIDIAPCIePrivacyRaspberry PiSEMICONDUCTORSK hynixSSDSwitchTIautomotivecoolingcybersecuritygamingiOSlaptopmemorymicrochipmonitorsoftware
about 1 year ago
➀ Electron Beam Probing (EBP) has become a powerful method for security analyzing of sub-7nm ICs. ➁ It offers better spatial resolution than optical probing and is suitable for sub-7nm flip-chips and advanced 3D architectures. ➂ The research focuses on the importance of EBP in failure analysis and hardware assurance.
2nm3nmAI chipAMDASUSDellEDAEUVGDDRGaNHPCICInfineonLinuxPCIePrivacyRaspberry PiSEMICONDUCTORSecuritySwitchautomotivecoolingcybersecuritygamingiOSlaptopmemorymicrochipmonitorsoftwaretechnology
about 1 year ago
➀ The research investigates the effects of adding TiC nanoparticles to aluminum alloy 7075, aiming to enhance casting performance and improve fluidity and surface quality; ➁ TiC nanoparticles were introduced in two concentrations, and their impact on fluidity and microstructure was analyzed; ➂ The results showed a significant improvement in fluidity and surface quality, with finer grain sizes and smoother surfaces.
2nm3D IC3nmAIAI ChipAMDArmAsusChipletCoolingDellEDAEMIBEUVGDDRGPUGaNHBMHPCInfineonLaptopLinuxMicrochipNPUNVIDIAPCIePrivacyRaspberry PiSSDSoftwareSwitchTIautomotivecpucybersecurityiosmemorymonitorsemiconductor
about 1 year ago
➀ Rapidus, the Japanese startup aiming for 2nm manufacturing capability, faces a $7 billion funding gap. Three Japanese banks are investing $35 million each, with the Development Bank of Japan adding $70 million. ➁ Rapidus originally estimated a $14 billion cost for its 2nm pilot line and $7 billion for volume production. Now, the company forecasts another $7 billion is needed to establish the pilot line, with the total estimated at $35 billion. ➂ Rapidus is seeking additional investment from corporate backers and government support for its expansion plans.
2nmJapanRapidusfundingsemiconductortechnology
over 1 year ago
1. Applied Materials introduces a new deposition tool that allows copper wires to be used in 2nm and more advanced process technologies. 2. The tool uses a binary RuCo liner to improve surface properties for copper reflow, reducing resistance by 25%. 3. The company also introduces an upgraded Black Diamond Low-K film to further reduce dielectric constant and increase mechanical strength for 3D stacking.
2nmApplied MaterialsCopper Wires
over 1 year ago
As part of Samsung's Q1 earnings announcement, the company has outlined some of its foundry unit's key plans for the rest of the year. The company has confirmed that it remains on track to meeting its goal of starting mass production of chips on its SF3 (3 nm-class, 2nd Generation) technology in the second half of the year. Meanwhile in June, Samsung Foundry will formally unveil its SF2 (2 nm-class) process technology, which will offer a mix of performance and efficiency enhancements. Finally, the company the company is preparing a variation of its 4 nm-class technology for integration into stacked 3D designs. SF2 To Be Unveiled In June Samsung plans to disclose key details about its SF2 fabrication technology at the VLSI Symposium 2024 on June 19. This will be the company's second major process node based upon gate-all-around (GAA) multi-bridge channel field-effect transistors (MBCFET). Improving over its predecessor, SF2 will feature a 'unique epitaxial and integration process,' which will give the process node higher performance and lower leakage than traditional FinFET-based nodes (though Samsung isn't disclosing the specific node they're comparing it to). Samsung says that SF2 increases performance of narrow transistors by 29% for N-type and 46% for P-type, and wide transistors by 11% and 23% respectively. Moreover, it reduces transistor global variation by 26% compared to FinFET technology, and cuts product leakage by approximately 50%. This process also sets the stage for future advancements in technology through enhanced design technology co-optimization (DTCO) collaboration with its customers. One thing that Samsung has not mentioned in context of SF2 is backside power delivery, so at least for the moment, there is no indication that Samsung will be adopting this next-gen power routing feature for SF2. Samsung says that the design infrastructure for SF2 – the PDK, EDA tools, and licensed IP – will be finalized in the second quarter of 2024. Once this happe
2nmGAASamsung