➀ Qualcomm hires Sailesh Kottapalli, a former Intel Xeon architect, to lead its data center CPU development; ➁ Kottapalli joins as a senior vice president, bringing 28 years of Intel experience; ➂ Qualcomm's new server CPUs will use cores from Nuvia, acquired in 2021.

➀ ARIA Sensing introduces the world's first 3D Ultra-Wideband Radar System-On-Chip (SoC), the 'Hydrogen', with advanced features like 3D beamforming and programmable bandwidth up to 1.8 GHz; ➁ The SoC offers dual RISC-V microprocessors for high-performance processing and flexibility; ➂ The company provides modular solutions for 2D and 3D radar applications across various industries.

➀ Cadence has introduced a new system chiplet based on Arm; ➁ The article delves into the motivations behind this move; ➂ The Briefing series provides further insights.

➀ DigiKey has added MediaTek to its linecard with a global distribution agreement; ➁ MediaTek's products available include development boards, kits, programmers, ICs, and RF and wireless products; ➂ MediaTek's portfolio includes SoCs for various applications such as IoT, embedded systems, and home entertainment.

➀ The complexity of SoC design validation due to hardware-software interactions; ➁ The exponential cost of fixing design bugs increases with each verification stage; ➂ Arm's SystemReady Certification Program simplifies the validation process by enhancing software compatibility and interoperability across devices.

➀ SoC design is prevalent in our daily lives; ➁ It powers a wide range of electronic devices from smartphones to automobiles; ➂ The demand for sophisticated and interconnected devices drives the growth of the semiconductor industry; ➃ SoC design is found in consumer electronics such as smartphones and tablets.

➀ Sondrel has launched a suite of IP blocks for SoC management, including PMU, URG, and UCG to control startup, clock, and power domains. ➁ The PMU manages the startup of the SoC, provides software control over reset trees, and handles system faults. ➂ The URG coordinates on-chip reset management for increasing logic complexity in SoCs. ➃ The UCG is responsible for on-chip clock management and supports multiple clock sources and references.

➀ Siemens has introduced a new In-System Test Controller, the ISTC, to enable deterministic in-system testing with the Tessent Streaming Scan Network software. ➁ The ISTC supports all Tessent MissionMode features and can target specific cell-internal and aging defects. ➂ The new product addresses challenges in safety and security, as well as quality in networking and data centers.

➀ The RISC-V and open-source functional verification challenge highlights the differences in verification processes between RISC-V and ARM cores. ➁ The importance of selecting a reliable IP vendor and the impact of software support on verification is discussed. ➂ The role of RISC-V profiles in simplifying verification and enabling software compatibility is emphasized.

➀ Asus shares official die shots of the Core Ultra 9 285K; ➁ Intel's Arrow Lake architecture and 3D Foveros packaging technology; ➂ Detailed breakdown of each tile's layout and functionality

➀ Apple is set to unveil its new M4 family of processors; ➁ The new MacBook Pros will be powered by the M4, M4 Pro, and M4 Max SoCs; ➂ TSMC's 3nm process node is used for the new processors.

➀ Korea’s September semiconductor exports reached a record high of $13.63 billion, up 36.3% year-on-year. Memory exports grew 60.7% year-on-year and 20% month-on-month to $8.72 billion. SoC exports rose 5.2% year-on-year to $4.37 billion. ➁ The overall Information and Communication Technology exports in September 2024 increased by 24% year-on-year to $22.36 billion. ➂ HBM had a significant impact on DRAM export values, and TrendForce forecasts that memory price growth will slow in Q4.

➀ Efabless and SensiML collaborate to offer chipIgnite ML, a new SoC platform that promises developers the ability to create custom silicon ten times more efficient than MCUs, expanding the potential for edge ML; ➁ The platform offers dedicated functionality accessible via SensiML's development tools, reducing development time and enhancing ML capabilities for edge applications; ➂ SensiML's AutoML platform allows embedded developers to create ultra-efficient sensor inference algorithms, while Efabless provides open-source tools for designing custom SoCs.

➀ Huawei's next flagship SoC is expected to use a 5nm Kirin chip, potentially closing the gap with Apple and Qualcomm's 3nm process nodes; ➁ The Chinese government and SMIC are reportedly fully supporting the development of this new chip; ➂ Huawei's past success with the 5nm Kirin 9000 5G AP shows that the company can compete with the industry's leading manufacturers.

➀ The article introduces the Pluto radar sensor reference design by NXP, a 28nm single-chip radar SoC; ➁ It highlights the high RF performance and flexibility of the design for various radar applications; ➂ The design is targeted for vehicle safety features like automatic cruise control and obstacle detection.

➀ VeriSilicon selects Arteris FlexNoC 5 interconnect IP for high-performance SoC design; ➁ The interconnect IP provides enhanced cost and design efficiency; ➂ The IP is physically aware and offers scalability.

➀ Intel presented four technical papers at Hot Chips 2024, detailing the Xeon 6 SoC, Lunar Lake client processor, Gaudi 3 AI accelerator, and OCI chiplet. ➁ The Xeon 6 SoC (Granite Rapids-D) is set to launch in the first half of 2025, featuring improved performance and efficiency. ➂ Intel highlighted advancements in AI applications across data centers, cloud, and edge computing, showcasing the industry's first fully integrated optical compute interconnect chiplet.

1. Defacto Technologies and ARM have developed a joint SoC design flow using Arm IP Explorer and Defacto’s SoC compiler. 2. This automated approach significantly reduces manual effort and speeds up the design process. 3. Defacto's tools support configuration with RISC-V cores and scripting languages like Python, Tcl, Java, Ruby, and C++. 4. The company's EDA spinout, Innova, predicts EDA license and compute resource needs using an AI engine.

1. Cadence introduces the Janus NoC IP to enhance its system IP portfolio, addressing complex interconnect challenges in SoCs. 2. The Janus NoC provides scalable architecture, efficient communication, and supports dynamic configurations for multi-chip and chiplet designs. 3. It leverages Cadence's extensive software and hardware offerings, ensuring high performance, power efficiency, and area optimization.

1. The article discusses the complexities of developing software for modern System on Chip (SoC) designs, highlighting the multi-layered software stack and the challenges in verification and validation. 2. It emphasizes the significant role of hardware-assisted verification platforms and virtual prototypes in overcoming these challenges. 3. The piece also underscores the importance of early software testing to avoid costly hardware respins and missed market opportunities.