Recent #EDA news in the semiconductor industry

6 months ago

➀ Infinisim, founded by Samia Rashid, specializes in SoC clock verification solutions for high-performance designs.

➁ In 2024, Infinisim capitalized on the growing demand for AI and data-intensive applications, focusing on clock performance and the challenges of timing jitter and reliability aging.

➂ For 2025, Infinisim anticipates growth driven by the rapid expansion of AI applications, emphasizing the need for precise design methodologies and reducing excessive margins to enhance performance and profitability.

AIEDAHPC
6 months ago

➀ Silicon Creations achieved significant milestones in 2024, including shipping over ten million wafers and reaching 1000 production licenses for its Fractional SoC PLL IP.

➁ The company specializes in mixed-signal IP solutions focusing on clocking and high-speed data interfaces, working with various foundries and advanced process nodes.

➂ In 2025, Silicon Creations anticipates growth in AI accelerator chips, crypto mining, and automotive sectors, driven by customer tapeouts in advanced nodes and early interest in sub-2nm nodes.

ChipletEDASilicon Creations
6 months ago

➀ Performance validation in SoC designs is distinct from architectural exploration, focusing on evaluating actual performance to meet specifications.

➁ Hardware-Assisted Verification (HAV) platforms play a crucial role in performance validation by enabling real-world traffic testing and firmware performance tuning.

➂ Part 2 of 2 explores the performance validation process across hardware blocks and firmware in SoC designs, emphasizing the critical role of HAV platforms.

ChipletEDAHPC
6 months ago

➀ Sarcina Technology, led by Founder and CEO Larry Zu, offers comprehensive post-silicon ecosystem services including package design, assembly, testing, qualification, and production services for leading semiconductor companies.

➁ In 2024, Sarcina developed a Bump Pitch Transformer (BPT) to simplify and reduce costs in 2.5D package designs, addressing challenges related to costly silicon TSV interposers.

➂ Sarcina aims to increase awareness of its capabilities, especially its Application Specific Advanced Package (ASAP) Service, through presentations and participation in industry conferences.

ChipletEDAHPC
6 months ago

➀ Defacto Technologies, led by Dr. Chouki Aktouf, specializes in innovative SoC design solutions and has become a leader in front-end SoC integration.

➁ In 2024, the company focused on incorporating AI technologies into their R&D projects, aiming to introduce AI-based automation in their tools.

➂ For 2025, the company plans to focus on AI-based EDA and attend key industry conferences like DAC and DATE.

AIChipletEDAHPCSoC
6 months ago

➀ Traditional flash memory is inadequate for modern non-volatile storage needs, leading to the rise of MRAM and RRAM.

➁ Synopsys offers flexible, IP-based compiler solutions for embedded memory, enabling design teams to optimize memory configurations for various applications.

➂ Synopsys collaborates with leading foundries to advance MRAM and RRAM technologies and integrate them into semiconductor designs.

EDAIP-Based CompilersMRAMRRAMmemory
6 months ago
➀ 35ELEMENTS致力于通过开发立方氮化镓半导体材料来帮助实现碳中和;➁ 公司计划在两年内在兼容CMOS的Si(100)衬底上扩大其材料规模,并寻求与代工厂的合作;➂ 35ELEMENTS拥有立方氮化镓材料的独家专利,并计划制造高效的光发射器,如创新型绿色发光二极管。
2nm3D IC3nmAIAI PCAI chipAMDASUSArmCPUChipletDRAMDellEDAEMIBEUVGDDRGPUGaNHBMHPCInfineonLinuxNPUNVIDIAPCIePrivacyRaspberry PiSEMICONDUCTORSK hynixSSDSwitchTIautomotivecoolingcybersecuritygamingiOSlaptopmemorymicrochipmonitorsoftware
7 months ago
➀ Intel's Foundry Services (IFS) division is struggling with low wafer yields and projected cumulative losses. ➁ Selling IFS could provide Intel with $30 billion to focus on core operations, but might hinder IDM 2.0 strategy. ➂ The decision hinges on whether Intel should continue investing in IFS or sell it to reduce financial risks.
EDAFoundry ServicesIFSIntelManufacturingSEMICONDUCTORtechnology
7 months ago
➀ Intel's shift to a more transparent strategy in technology announcements; ➁ The competition between Intel's PowerVia and TSMC's Super Power Rail; ➂ Andy Grove's philosophy of maintaining a 'healthy amount of paranoia'.
2nm3D IC3nmAIAI PCAI chipAMDASUSArmCPUChipletDRAMDellEDAEMIBEUVGDDRGPUGaNHBMHPCInfineonLinuxNPUNVIDIAPCIePrivacyRaspberry PiSEMICONDUCTORSK hynixSSDSwitchTIautomotivecoolingcybersecuritygamingiOSlaptopmemorymicrochipmonitorsoftware
7 months ago
➀ The complexities of modern IC designs with multiple clocks and asynchronous resets make reset logic more challenging than in early single-clock designs; ➁ Reset Domain Crossing (RDC) tools, like Questa RDC, perform static verification on reset logic to identify issues like glitches and metastability; ➂ Siemens' Questa RDC is effective in identifying structural and advanced reset tree issues, ensuring integrity before tapeout.
EDAIC DesignQuesta RDCReset LogicSiliconStatic Analysisverification