SemiVoice

➀ Texas Instruments' TIDA-00757 reference design tackles smart locks' battery drain using BLE and low-power motor drivers;

➁ Integrates ultra-low-power MCU, efficient DC/DC converter, and motor current limiting for extended battery life up to 5+ years;

➂ Supports wireless control and battery monitoring, applicable in building automation, security systems, and HVAC actuators.

➀ The Microtest Group introduced Quasar200 and Pulsar600 testing systems for efficient semiconductor device validation;

➁ Quasar200 provides precise DC/AC measurements for Si, GaN, and SiC devices, while Pulsar600 supports high-current automotive and industrial applications up to 1,000 A DC;

➂ Both systems feature plug-and-play setups, safety protections, and ±0.1% measurement accuracy to streamline testing processes.

➀ Upbeat Technology and SiFive collaborate on a dual-core RISC-V MCU family (UP201/UP301) featuring AI accelerators for ultra-low-power edge AI applications.

➀ Delivers 16.8 μW/MHz/DMIPS energy efficiency, 400 MHz clock speed, and advanced error correction for resilient near-threshold operation in wearables, drones, and IoT systems.

➂ Live demos at RISC-V Summit highlight performance, with engineering samples and SDKs available to enable next-gen battery-optimized AI designs.

➀ Samsung purchased two high-NA EUV machines (Twinscan EXE:5200B) for $773 million to boost 2nm chip production, with deliveries planned for 2025 and early 2026;

➁ The machines, installed at Hwaseong R&D facility, will support 2nm foundry processes for Exynos processors and Tesla's ADAS chips, achieving transistor sizes down to 8nm;

➂ TSMC has delayed high-NA EUV adoption until 1.4nm processes, while Qualcomm and MediaTek consider shifting 2nm orders to Samsung due to TSMC's higher wafer costs ($30k per wafer).

➀ Infineon is sampling 60GHz CMOS radar sensors (BGT60CUTR13AIP) for ultra-low power IoT applications, targeting Physical AI enhancement in smart home devices;

➁ The sensor integrates on-chip processing, 7GHz bandwidth, and 20m detection range, supporting presence/gesture sensing while reducing host processor load;

➂ Applications include security cameras and HVAC systems, with features like autonomous wake-up and privacy-focused activity monitoring enabled by dedicated software stacks.

➀ JEDEC announced version 1.4 of the DDR5 SPD Contents standard (JESD400-5D), enhancing memory initialization and optimization for BIOS;

➁ The update adds support for DDR5-9200 speeds, introduces codes for SOCAMM2 modules, and expands error logging for MRDIMMs;

➂ The standard applies to all DDR5 modules, reflecting JEDEC's role in unifying industry solutions with input from 360 member companies.

➀ AMD showcased its Helios MI450 AI reference rack at OCP Summit 2025, featuring power shelves, compute nodes, and networking trays, designed by the ZT Systems team acquired by AMD;

➁ Meta presented a modified version of the Helios rack at the event, with significant differences in power distribution, networking layouts, and component configurations;

➂ The rack highlights AMD's focus on AI/HPC infrastructure, including PCIe Gen6 support and EDSFF E1.S SSDs, with the system's design optimized for high-density AI workloads.