➀ JEDEC and OCP announce new Chiplet Design Kits for EDA use;
➁ The kits cover Assembly, Substrate, Material, and Test;
➂ The kits aim to automate SiP design and build using chiplets.
Recent #JEDEC news in the semiconductor industry
➀ JEDEC发布JESD220G: Universal Flash Storage 4.1，是UFS标准的更新；➁ UFS 4.1针对功率效率至关重要的应用提供更快的数据访问和改进的性能；➂ JEDEC还更新了互补的JESD223F UFS主机控制器接口（UFSHCI）标准。
➀ JEDEC has published JESD230G, a new NAND Flash Interface Interoperability Standard; ➁ The standard supports speeds up to 4,800 MT/s, a significant increase from the previous version; ➂ JESD230G introduces a separate Command/Address Bus Protocol (SCA) for improved efficiency.
1. JEDEC is developing standards for DDR5 MRDIMMs and LPDDR6-based CAMMs. 2. MRDIMMs aim to double peak bandwidth to 12.8 Gbps and support more than two ranks. 3. LPDDR6 CAMMs will feature a new connector array to accommodate wider memory bus requirements.
1. The desktop memory market is set to introduce a new type of DIMM called Clocked Unbuffered DIMM (CUDIMM) to enhance performance. 2. CUDIMMs address signal integrity challenges of DDR5 by adding a clock driver to the DIMM, improving stability and reliability at high speeds. 3. Standardized by JEDEC, CUDIMMs are designed for DDR5-6400 speeds and higher, and are compatible with existing platforms.
➀ JEDEC has announced the PS-007A LPDDR5 CAMM2 Connector Performance Standard for compact form factor devices. ➁ The standard offers a standardized modular LPDDR5 solution with ecosystem support. ➂ It highlights benefits like improved signal integrity, lower power consumption, and reduced form factor.
1. JEDEC has announced plans for advanced memory modules including DDR5 Multiplexed Rank Dual Inline Memory Modules (MRDIMM) and a next-generation Compression-Attached Memory Module (CAMM) for LPDDR6 to support high-performance computing and AI applications. 2. The MRDIMM standard aims to double the bandwidth to 12.8 Gbps and increase the pin speed, supporting more than two ranks and ensuring compatibility with conventional RDIMM systems. 3. The next-generation CAMM module for LPDDR6 targets a maximum speed greater than 14.4 GT/s, offering a 24-bit subchannel, a 48-bit channel, and a connector array.
1. JEDEC has released JESD405-1B, a standard for CXL memory module labels, detailing information like memory type, protocol revision, and capacity. 2. The standard supports SNIA EDSFF form factors E1.S and E3.S, and includes connector and I/O configuration details. 3. JESD405-1B, along with JESD317A, aims to support and expand the CXL market by ensuring multiple sourcing options for CMMs.