➀ Intel and Cadence collaborate to advance the UCIe standard, focusing on multi-die design and interoperability. ➁ The collaboration aims to address technical challenges in UCIe compliance and pre-silicon interoperability. ➂ The white paper details the strategies and technical advancements in building an open chiplet ecosystem.

➀ UCIe standardizes chiplet communication, lowering barriers and fostering innovation. ➁ It enables specialized and customized solutions by allowing mix-and-match of chiplets from various vendors. ➂ UCIe supports custom silicon for AI applications, enhancing performance and efficiency.

Qualtias Semiconductor said on Tuesday that it will raise 59.5 billion won through a share offering.Out of the total, 57.5 billion won will be spent up to 2027 for the research and development of new chip IPs, the company said,49.5 billion won will be spent on next-generation products and the applic

➀ Introduction to UCIe 2.0 specification; ➁ Potential to solve technical and business challenges in chiplet integration; ➂ Impact on the future of chiplet technology.

1. Alphawave Semi claims to have successfully brought up the first 3nm UCIe Die-to-Die (D2D) IP with TSMC's CoWoS advanced packaging technology. 2. The complete PHY and Controller subsystem was developed in collaboration with TSMC, targeting applications like hyperscaler, HPC, and AI. 3. The IP supports multiple protocols and integrates live per-lane health monitoring, setting a new benchmark in high-performance connectivity solutions.

1. Alphawave Semi has announced the tape-out of an industry-first IO chiplet on TSMC's 7nm process, supporting UCIe, Ethernet, PCIe, and CXL. 2. The chiplet delivers a total bandwidth of up to 1.6Tbit/s and supports multiple standards including PCIe 6.0, CXL 3.x, and 800G Ethernet. 3. The company highlights the flexibility and scalability this chiplet provides for hyperscaler and datacenter infrastructure customers, allowing them to mix and match custom SoCs with I/O connectivity or memory expansion chiplets.