➀ Ansys and Synopsys announce the sale of Ansys PowerArtist business to Keysight Technologies; ➁ The transaction involves the sale of semiconductor design and simulation software; ➂ The deal is subject to regulatory approvals.

➀ The growing demand for AI infrastructure requires scalable interconnects; ➁ Ultra Ethernet and UALink address the challenges of scaling AI acceleration clusters; ➂ Synopsys' IP solutions offer efficient and power-efficient interconnects for data centers.

➀ Synopsys announces Ultra Ethernet and UALink IP for next-generation AI datacenters; ➁ The IPs support high-speed connectivity and intelligent multipathing; ➂ The technologies are expected to be launched in 2025.

➀ Rapidus and Synopsys collaborate to shorten the IC design cycle with a new approach; ➁ The approach aims to reduce the need for re-characterization and accelerate design iterations; ➂ Synopsys will develop advanced design flows and enable a broad IP portfolio on Rapidus’ 2nm GAA process.

➀ Synopsys addresses the challenges of multi-die integration with its 3DIO IP Solution and 3DIC tools; ➁ The 3DIO IP Solution includes synthesis-friendly Tx/Rx cells and a high data rate solution; ➂ Synopsys' tools enable faster timing closure and reduced bit error rates in multi-die designs.

➀ The rise of 2.5D and 3D multi-die design in mainstream applications; ➁ Comprehensive design flows provided by Synopsys and Ansys for multi-die projects; ➂ Expert insights from Marc Swinnen and Keith Lanier on technical knowledge and engaging presentation.

➀ Alchip presents at TSMC OIP Ecosystem Forum; ➁ Challenges in 3D IC design overcome; ➂ Collaboration with Synopsys and TSMC for 3D design innovation

➀ The rise of 2.5D and 3D multi-die designs driven by high-performance computing and AI; ➁ Challenges in architecture and early prototyping, including thermal management and mechanical reliability; ➂ The importance of early verification to prevent costly delays and suboptimal performance; ➃ The role of AI in optimizing design processes and outcomes; ➄ The significance of sign-off tools for ensuring reliability and longevity of multi-die designs.

➀ Aart de Geus, Synopsys' founder and chairperson, receives the SIA 2024 Robert N. Noyce Award for his pioneering contributions to the EDA technology over the past four decades; ➁ Synopsys has grown from an EDA tool provider to a global leader in EDA/IP, offering a comprehensive range of solutions; ➂ The company emphasizes innovation, with Synopsys.ai and digital twin technology, and a vast IP portfolio to support cutting-edge technologies like AI and smart manufacturing; ➃ Synopsys has been investing in China for nearly 30 years, collaborating closely with local industry and providing advanced design methodologies; ➄ The company continues to drive technological innovation and talent development, aiming to foster the next generation of 'chip' innovators.

➀ Synopsys reported revenue of $1.526 billion for the third quarter of fiscal year 2024, up from $1.354 billion in the same period last year.; ➁ The company expects a record year based on its strong third quarter performance.

➀ Synopsys reported a 13% increase in revenue for Q3 2024, reaching $1.526 billion. ➁ The company expects a record full-year revenue with around 15% growth. ➂ Sassine Ghazi, CEO of Synopsys, attributed much of the growth to the increased use of AI in technology innovation.

➀ Synopsys will host the IP Processor Summit 2024 in Santa Clara, focusing on RISC-V solutions for IoT and automotive applications. ➁ The keynote speaker, Alexander Kocher, CEO of Quantauris, will discuss the benefits and challenges of RISC-V adoption. ➂ The event will provide in-depth information on ARC-V™ RISC-V processor IP and other related technologies.

1. Synopsys introduces the industry's first complete PCIe 7.0 IP solution, designed to meet the increasing demands of AI and high-performance computing. 2. The solution features doubled bandwidth and support for linear direct drive optics, enhancing signal integrity and performance. 3. Synopsys' early access program and complete solution approach ensure robust, reliable technology ahead of mainstream adoption.

1. Sashi Obilisetty, Executive Director of R&D at Synopsys, received the Marie R. Pistilli Women in Engineering Achievement Award at DAC 2024. 2. The award honors individuals who have significantly contributed to advancing women in electronic design. 3. Obilisetty is recognized for her entrepreneurial achievements and her role in integrating AI into Synopsys' products.

1. Synopsys has certified its AI-driven digital and analog design flows on Samsung's 2nm SF2 process with multiple test chip tapeouts. 2. The collaboration enhances performance, power efficiency, and area optimization, and accelerates analog design migration for Samsung's latest Gate-All-Around (GAA) process technologies. 3. Synopsys and Samsung are closely collaborating on AI-driven flows to optimize design productivity and PPA, and to enable efficient analog design migration.

Data communication speeds continue to grow. New encoding schemes, such as PAM-4 are helping achieve faster throughput. Compared to the traditional NRZ scheme, PAM4 can send twice the signal by using four levels vs. the two used in NRZ. The diagram at the top of this post shows the how data density is increased. With progress comes… Read More The post Synopsys is Paving the Way for Success with 112G SerDes and Beyond appeared first on SemiWiki.

This week Samsung Electronics and Synopsys announced that Samsung has taped out its first mobile system-on-chip on Samsung Foundry's 3nm gate-all-around (GAA) process technology. The announcement, coming from electronic design automation Synopsys, further notes that Samsung used the Synopsys.ai EDA suite to place-n-route the layout and verify design of the SoC, which in turn enabled higher performance. Samsung's unnamed high-performance mobile SoC relies on 'flagship' general-purpose CPU and GPU architectures as well as various IP blocks from Synopsys. SoC designers used Synopsys.ai EDA software, including the Synopsys DSO.ai to fine-tune design and maximize yields as well as Synopsys Fusion Compiler RTL-to-GDSII solution to achieve higher performance, lower power, and optimize area (PPA). And while the news that Samsung has developed a high-performance SoC using the Synopsys.ai suite is important, there is another, even more important dimension to this announcement: this means that Samsung has finally taped out an advanced smartphone application processor on its cutting-edge 3nm GAAFET process. Although Samsung Foundry has been producing chips on its GAA-equipped SF3E (3 nm-class, 'early' node) process for almost two years now, Samsung Electronics has never used this technology for its own system-on-chips for smartphones or other complex devices. To date, SF3E has been used mainly for cryptocurrency mining chips, presumably due to the inevitable early teething and yield issues that come with being the industry's first commercial GAAFET process. For now, Samsung isn't disclosing what specific process node is being used for the SoC; the official Samsung/Synposys announcement only notes that it's for a GAA process node. Along with their first-generation 3nm-class SF3E, Samsung Foundry has a considerably more sophisticated SF3 manufacturing technology that offers numerous improvements over SF3E, and is due to be used for mass production in the coming quarters. Given th