1. Synopsys introduces the industry's first complete PCIe 7.0 IP solution, designed to meet the increasing demands of AI and high-performance computing. 2. The solution features doubled bandwidth and support for linear direct drive optics, enhancing signal integrity and performance. 3. Synopsys' early access program and complete solution approach ensure robust, reliable technology ahead of mainstream adoption.

➀ PCIe 7.0 external cable specifications are under discussion and update, with a focus on signal integrity. ➁ The differential insertion loss for PCIe 7.0 cables is required to reach 48GHz. ➂ Return loss is specified to be -15dB at 32GHz. ➃ Near-end and far-end crosstalk requirements are provided without specifying ICN. ➄ Cable skew and lane-to-lane skew are also defined, with EIPS less than 2ps and lane-to-lane skew less than 200ps for cables up to 1m.

1. Compliance tests for PCIe 6.0 and PCIe 7.0 have been delayed by PCI-SIG. 2. This delay could potentially slow down the adoption of these technologies. 3. The roadblock in the standards development may impact the broader technology industry.