Recent #Signal Integrity news in the semiconductor industry

7 months ago
➀ Signal Integrity (SI) issues in PCB and package design; ➁ Waveform distortions and time delays; ➂ Types of signal integrity problems like overshoot and ISI; ➃ Transmission line modeling and microstrip/stripline examples; ➄ Minimizing discontinuities and managing reflections; ➅ Mitigating crosstalk and via performance; ➆ Timing and skew considerations in high-speed digital designs.
Cross TalkDifferential PairsEDAHyperLynxISIImpedanceOvershootPCB DesignSignal IntegritySimulationTimingViaselectronics
2 months ago

➀ This article discusses a reference design for extending SPI communication range using LVDS interface, which improves signal quality, reduces EMI, and maintains robustness against noise.

➁ The design utilizes TI's TIDA-060017 reference design, featuring LVDS driver and receiver modules, to transmit SPI signals over longer distances.

➂ The solution offers advantages such as enhanced speed, lower power consumption, and compatibility with a variety of industrial and medical applications.

DesignEDAMicrochipPCBSignal Integrity
2 months ago

➀ Keysight Technologies has introduced two oscilloscopes designed for testing 1.6T optical transceivers: a single optical channel DCA-M and a dual optical channel DCA-M Sampling Oscilloscope. These instruments are engineered for high optical measurement sensitivity and integrated clock recovery.

➁ The oscilloscopes feature ultra-low optical channel noise and minimal intrinsic jitter, ensuring accurate high-data-rate analysis with jitter below 90 fs. They simplify test setup and compliance assurance while optimizing production efficiency.

➂ Keysight's advanced oscilloscopes support high-speed optical signal analysis and are expected to accelerate AI-driven data center innovations by providing precise measurements for 1.6T transceivers.

AIData centerKeysight TechnologiesSignal Integrity
8 months ago

➀ Signal integrity and noise management become more critical at higher frequencies, complicating traditional testing methods.

➁ Advanced testing techniques like over-the-air (OTA) testing are being used to ensure precise fault detection.

➂ The need for high-speed serial interfaces like PCIe and SerDes is growing to test high-functional frequencies.

➃ Boutique design houses face challenges due to the cost and availability of advanced testing equipment.

➄ AI and machine learning are being explored for data analysis and predictive maintenance.

➅ Balancing cost and test accuracy remains a significant challenge.

➆ 6G technology promises unprecedented data transfer speeds, but also brings new technical challenges.

➇ Standards are crucial for ensuring compliance and interoperability in high-frequency testing.

Signal Integrity
9 months ago
➀ PCIe 7.0 external cable specifications are under discussion and update, with a focus on signal integrity. ➁ The differential insertion loss for PCIe 7.0 cables is required to reach 48GHz. ➂ Return loss is specified to be -15dB at 32GHz. ➃ Near-end and far-end crosstalk requirements are provided without specifying ICN. ➄ Cable skew and lane-to-lane skew are also defined, with EIPS less than 2ps and lane-to-lane skew less than 200ps for cables up to 1m.
Cable SpecificationsPCIe 7.0Signal Integrity
10 months ago
➀ DDR5 continues to increase data rates, using single-ended data lines and considering DFE at the DRAM side to mitigate signal integrity issues. ➁ Differences between DDR5 and SerDes include the number of links and channel lengths, with DDR5 being multipoint and shorter. ➂ Equalization techniques like CTLE, DFE, and FFE are used to compensate for channel losses and dispersion, with DFE being particularly effective for DDR5 due to its susceptibility to reflections. ➃ Simulation results show that while equalization is not always necessary, it is crucial for certain configurations involving DIMM slots and higher data rates.
EqualizationSignal Integrityddr5