➀ TSMC's N3 process is expected to be a long-running and high volume node, referred to as 'the last and best finfet node' by Kevin Zhang, SVP for Business Development and Overseas Operations Office.

➁ The N3 process includes multiple variants such as N3B, N3E, N3P, N3X, N3S, N3RF, N3A, and N3C, each tailored for different applications.

➂ TSMC's strategy is to develop a comprehensive and customizable silicon resource with the N3 process, aiming to make integrated silicon performance a platform.

➀ TSMC is advancing the production start date for its second Arizona fab, Fab 21, by at least two quarters; the original plan was set for 2028.

➁ Fab 21 is being equipped for a 3nm process, with modules for 2nm and 1.6nm processes to begin construction this year, with production expected in 2029.

➂ TSMC CEO CC Wei states that the expansion will create an independent leading-edge semiconductor manufacturing cluster in the U.S., contributing to a more comprehensive supply chain ecosystem.

➀ TSMC plans to produce 30% of its N2 (2nm-class) output in the U.S., making its Fab 21 site an independent semiconductor manufacturing cluster.

➁ TSMC aims to accelerate the construction of new Fab 21 modules to produce chips on N3 (3nm-class), N2, and A16 (1.6nm-class) nodes.

➂ Around 30% of TSMC's N2 and A16 chips produced in the U.S. will be a significant development.

➀ Ferroelectric Memory Co. (FMC) and Neumonda are reestablishing DRAM+ production in Germany.

➁ The new DRAM+ memory uses FeRAM technology with hafnium oxide for non-volatility and high capacity.

➂ FMC's technology aims to improve energy efficiency and data retention while maintaining DRAM performance.

➀ DeteQt，一家传感初创公司，已从澳大利亚的Main Sequence Ventures和ATP Fund获得750,000美元的种子前融资。

➁ DeteQt是悉尼大学纳米研究所的衍生公司，其拥有一种‘钻石硅’技术，用于制造量子磁力计。

➂ 该公司的CEO，悉尼大学兼职教授Jim Rabeau，将在本周的量子澳大利亚会议上宣布这项投资。

➀ Imec and Zeiss have signed a Strategic Partnership Agreement to advance semiconductor technology.

➁ The partnership focuses on High-NA-EUV lithography and other key semiconductor manufacturing technologies.

➂ Zeiss will support imec with research projects and lithography optics, enhancing imec's pilot line capabilities.

➀ Intel's 18A process is reported to have a yield of 20-30% by analyst Ming-Chi Kuo;

➁ This low yield will delay the release of Panther Lake processors for notebooks, impacting Intel's financials and customer confidence;

➂ Notebook manufacturers may use limited qualification samples to introduce Panther Lake into products, as TSMC's 2nm process yields are higher than Intel's 18A.

➀ TSMC announced a $100 billion investment plan in the US, including the construction of 5 new chip factories over the next few years;

➁ The new investment includes 3 chip manufacturing plants and 2 advanced packaging factories, as well as a large-scale R&D center in the US;

➂ Trump emphasized the importance of chip and semiconductor manufacturing within the US for national security;

➃ TSMC promises to create 40,000 construction jobs in the US over the next four years;

➄ TSMC began producing 4nm chips for US customers in Arizona and has agreed to produce 2nm chips in its second Arizona factory, set to start production in 2028.

➀ Intel has begun production with the first two of ASML's advanced lithography machines in its factory, showing early data indicating increased reliability over earlier models.

➁ Intel, which became the first chip manufacturer to receive these machines last year, plans to use them to develop 18A manufacturing technology for mass production later this year.

➂ Imec has demonstrated the first electrical yield results from 20nm spacing metal lines patterned using High NA EUV single patterning technology, showing good electrical yield and fewer random defects.

➀ The demand for advanced node chips supporting AI is growing rapidly, putting pressure on the industry to meet demand;

➁ EUV lithography technology is critical for manufacturing these chips, and its stability requires continuous investment and improvement;

➂ The ongoing research and development in various aspects, from new photoresists to more powerful light sources, aims to improve the cost-effectiveness of EUV.

➀ An Intel insider, Joseph Bonetti, disputes recent rumors about Intel's struggles and its potential partnership with TSMC, arguing that Intel is making significant progress in semiconductor manufacturing.

➁ Bonetti highlights Intel's 3nm and 2nm process technologies, noting that Intel 3 is already in production and the next-generation Intel 18A is nearing completion.

➂ He emphasizes Intel's lead in High-NA EUV lithography, which is crucial for 1nm-level advanced processes.

➃ Despite financial difficulties, Bonetti believes Intel Foundry will prove itself with its products and attract major customers like Microsoft and Amazon.

➄ He warns against giving TSMC control over Intel's wafer fabs, emphasizing the potential damage to Intel and the US leadership position.

➀ Intel principal engineer expresses concern over TSMC's potential takeover of Intel Foundry.

➁ He highlights Intel's 18A technology advantage and advancements in semiconductor manufacturing.

➂ Bonetti argues against the notion that TSMC engineers are necessary for Intel's latest process technologies.

➀ Intel needs to fill all its fabs to maintain competitiveness in the semiconductor manufacturing field;

➁ TSMC is rapidly expanding its competitive advantage through partnerships with Japan and Europe;

➂ Creating a universal foundry platform alliance would allow other fabs to utilize their manufacturing capabilities, benefiting Intel;

➃ Intel's failed acquisition of Tower Semiconductor due to regulatory hurdles is a missed opportunity;

➄ TSMC's collaboration with Japanese and European companies to build fabs is a strategic move;

➅ Intel needs to transform and consider establishing a universal foundry platform alliance to fill its fabs and packaging facilities.

➀ The importance of photoresist in semiconductor manufacturing and the necessity for resolution scaling to utilize new architectures and materials.

➁ The discussion on yield challenges, particularly with edge placement error (EPE) and line edge roughness (LER), and the need for improved understanding and tools to mitigate these issues.

➂ The introduction of directed self-assembly (DSA) as a strategy to reduce line/space photoresist correction errors and its application in 18 nm and 21 nm metal pitch.

➃ The need for new photoresists to match node processes at 12 nm pitch and the impact of defect density on EUV chip cost.

➄ The importance of high-throughput experimental methods, chemical analysis of random defects, and 3D length scale detection in process change exploration.

➅ The industry's demand for high quantum yield photoresists, defect formation analysis, and dry development techniques for organic photoresists.

➀ The evolution of EUV photolithography gel from the 1970s to the present day, including various materials research.

➁ The unique aspects of EUV photolithography, such as short-wavelength manufacturing, special reflective optical systems, and special material systems.

➂ Common types of EUV photolithography gel, including chemical amplification, inorganic, non-chemical amplification, and hybrid gel.

➃ The main challenges in the development of EUV photolithography gel, such as sensitivity, resolution and LER, outgassing, and thermal stability.

➀ NXP and World Advanced are constructing a 12-inch wafer factory in Singapore with an investment of 7.8 billion USD, aiming to start mass production in 2027 and reach a monthly capacity of 55,000 12-inch wafers by 2029.

➁ NXP is actively seeking to establish a supply chain in China to serve customers needing Chinese production capacity.

➂ NXP plans to move some chip front-end manufacturing to China and establish a complete Chinese supply chain.