➀ Imec and Zeiss have signed a Strategic Partnership Agreement to advance semiconductor technology.
➁ The partnership focuses on High-NA-EUV lithography and other key semiconductor manufacturing technologies.
➂ Zeiss will support imec with research projects and lithography optics, enhancing imec's pilot line capabilities.
➀ ASML and imec have signed a new strategic partnership agreement, focusing on research and sustainability.
➁ The agreement aims to deliver valuable solutions in two areas: advancing the semiconductor industry and developing sustainable innovation initiatives.
➂ The collaboration includes ASML's full product portfolio, focusing on high-end nodes and advanced technologies.
➀ Intel has begun production with the first two of ASML's advanced lithography machines in its factory, showing early data indicating increased reliability over earlier models.
➁ Intel, which became the first chip manufacturer to receive these machines last year, plans to use them to develop 18A manufacturing technology for mass production later this year.
➂ Imec has demonstrated the first electrical yield results from 20nm spacing metal lines patterned using High NA EUV single patterning technology, showing good electrical yield and fewer random defects.
➀ SRAM has been used in high-performance computing architectures as embedded cache for decades, but its bit density expansion has slowed down and is affected by standby power issues.
➁ Spin Orbit Torque (SOT) MRAM offers advantages like low standby power, GHz-level switching speed, negligible leakage, almost infinite endurance, high reliability, and scalability, making it a promising alternative to SRAM.
➂ SOT-MRAM uses magnetic tunnel junctions (MTJ) as its basic building block, where the magnetic orientation can be vertical or in-plane, affecting the read and write operations.
➃ Recent advancements in SOT-MRAM technology, including improvements by imec, have demonstrated high switching speeds and durability, addressing key challenges in cache applications.
➄ Imec has developed innovative solutions for field-free switching, low dynamic power consumption, and scaling SOT-MRAM devices to the limit, making it a milestone for high-density SRAM applications.
➅ Further optimization of performance and reliability parameters, such as retention rate and write error rate, is being explored to bring SOT-MRAM closer to real-world specifications.
➆ Imec has also presented a novel composite free layer for MTJ, which improves the reliability of SOT-MRAM devices and reduces sensitivity to external magnetic disturbances.
➀ SRAM has been used in high-performance computing architectures as embedded cache for decades, but its bit density expansion has slowed down and is affected by standby power issues.
➁ Spin Orbit Torque (SOT) MRAM offers advantages like low standby power, GHz-level switching speed, negligible leakage, almost infinite endurance, high reliability, and scalability, making it a promising alternative to SRAM.
➂ SOT-MRAM uses magnetic tunnel junctions (MTJ) as its basic building block, where the magnetic orientation can be vertical or in-plane, affecting the read and write operations.
➃ Recent advancements in SOT-MRAM technology, including improvements by imec, have demonstrated high switching speeds and durability, addressing key challenges in cache applications.
➄ Imec has developed innovative solutions for field-free switching, low dynamic power consumption, and scaling SOT-MRAM devices to the limit, making it a milestone for high-density SRAM applications.
➅ Further optimization of performance and reliability parameters, such as retention rate and write error rate, is being explored to bring SOT-MRAM closer to real-world specifications.
➆ Imec has also presented a novel composite free layer for MTJ, which improves the reliability of SOT-MRAM devices and reduces sensitivity to external magnetic disturbances.
➀ Intel, TSMC, and Samsung are advancing their processes to 1.8nm (18A) and 1.6nm (16A) with full-gate transistors (Intel calls them RibbonFET) and further to the 14A node.
➁ Imec is researching the next-generation complementary field-effect transistor (CFET) stacked transistors on the process roadmap.
➂ Imec will showcase its CFET standard cell at the 2024 IEEE International Electronic Devices Meeting (IEDM) this week, which includes two rows of CFET with a shared signal wiring wall, reducing the area of logic and SRAM units significantly.
➃ Intel has made breakthroughs in 2D transistor technology using beyond-silicon materials, chip interconnects, and packaging technologies.
➄ Intel's RibbonFET is the company's first new transistor design since the introduction of FinFET 13 years ago and is the company's first full-gate (GAA) transistor.
