Recent #SRAM news in the semiconductor industry

➀ SRAM has been used in high-performance computing architectures as embedded cache for decades, but its bit density expansion has slowed down and is affected by standby power issues.

➁ Spin Orbit Torque (SOT) MRAM offers advantages like low standby power, GHz-level switching speed, negligible leakage, almost infinite endurance, high reliability, and scalability, making it a promising alternative to SRAM.

➂ SOT-MRAM uses magnetic tunnel junctions (MTJ) as its basic building block, where the magnetic orientation can be vertical or in-plane, affecting the read and write operations.

➃ Recent advancements in SOT-MRAM technology, including improvements by imec, have demonstrated high switching speeds and durability, addressing key challenges in cache applications.

➄ Imec has developed innovative solutions for field-free switching, low dynamic power consumption, and scaling SOT-MRAM devices to the limit, making it a milestone for high-density SRAM applications.

➅ Further optimization of performance and reliability parameters, such as retention rate and write error rate, is being explored to bring SOT-MRAM closer to real-world specifications.

➆ Imec has also presented a novel composite free layer for MTJ, which improves the reliability of SOT-MRAM devices and reduces sensitivity to external magnetic disturbances.

Imec SRAM memory

weixin

5 months ago

Alternative to SRAM: The New Choice!

➀ SRAM has been used in high-performance computing architectures as embedded cache for decades, but its bit density expansion has slowed down and is affected by standby power issues.

➂ SOT-MRAM uses magnetic tunnel junctions (MTJ) as its basic building block, where the magnetic orientation can be vertical or in-plane, affecting the read and write operations.

➃ Recent advancements in SOT-MRAM technology, including improvements by imec, have demonstrated high switching speeds and durability, addressing key challenges in cache applications.

➅ Further optimization of performance and reliability parameters, such as retention rate and write error rate, is being explored to bring SOT-MRAM closer to real-world specifications.

➆ Imec has also presented a novel composite free layer for MTJ, which improves the reliability of SOT-MRAM devices and reduces sensitivity to external magnetic disturbances.

Imec SRAM memory

electronicsweekly

5 months ago

sureCore taps Sarcina for cryo packaging

➀ SureCore has developed a custom BGA package for cryogenic temperatures in partnership with Sarcina. This package is designed for extreme low temperature operations. ➁ SureCore aims to make Cryo-CMOS available for the Quantum Computing ecosystem with their CryoMem™ range of memory IP. ➂ The partnership will help QC companies design control/interface chips for cryogenic environments, improving the performance and scalability of quantum computers.

Design Quantum Computing SRAM semiconductor

tomshardware

6 months ago

TSMC shares deep-dive details about its cutting edge 2nm process node at IEDM 2024 — 35 percent less power, or 15% more performance

➀ TSMC unveiled details about its N2 (2nm-class) fabrication process at IEDM 2024; ➁ The new process promises a 24 to 35% power reduction or a 15% performance improvement at the same voltage; ➂ Key advancements include GAA nanosheet transistors and N2 NanoFlex design-technology co-optimization.

2nm process Microelectronics SRAM TSMC performance improvement semiconductor

electronicsweekly

7 months ago

Fable: The Ambitious Company

➀ The story is about an ambitious startup that entered the DRAM, SRAM, E2PROM, and microprocessor markets; ➁ The company built two fabs and produced successful memories and a unique microprocessor that was not adopted by major applications; ➂ Despite spawning many startups that adopted its approach, the company could not survive independently and was taken over. The moral is that uniqueness can be a negative.

DRAM SRAM Startup semiconductor

hardwareluxx

11 months ago

ARM to Accelerate SRAM to 7 GHz

1. ARM has introduced a concept called High Bandwidth Instance (HBI) at the VLSI Symposium 2024, featuring an 8T 1R1RW SRAM design that allows for simultaneous read and write operations. 2. The HBI includes a DDATA memory that simplifies the design of the L1 Data Cache and offers a latency advantage of 10 to 15 ps. 3. ARM has tested a 3 nm chip with 112 SRAM-HBI macro cells, achieving speeds of up to 7.74 GHz at 0.945 V and 3.13 GHz at 0.495 V.

Arm High-Bandwidth-Instance SRAM