1. ARM has introduced a concept called High Bandwidth Instance (HBI) at the VLSI Symposium 2024, featuring an 8T 1R1RW SRAM design that allows for simultaneous read and write operations. 2. The HBI includes a DDATA memory that simplifies the design of the L1 Data Cache and offers a latency advantage of 10 to 15 ps. 3. ARM has tested a 3 nm chip with 112 SRAM-HBI macro cells, achieving speeds of up to 7.74 GHz at 0.945 V and 3.13 GHz at 0.495 V.