➀ Codasip has announced the L730 RISC core designed for automotive safety and security, meeting ISO/SAE 21434 and ISO 26262 compliance up to ASIL D. The core includes optional safety features and security mechanisms. ➁ The L730 is available in pre-verified configurations with custom instruction extensions via Codasip Studio Fusion's Bounded Customization. ➂ The core supports RISC-V Scalar Crypto Extension and CHERI for advanced memory safety. Custom Compute is enabled by Codasip Studio Fusion, allowing for optimized processors for specific applications.

➀ Jianxin Technology remains optimistic about the future applications of the RISC-V architecture across various fields, particularly in AI, automotive electronics, and IoT. ➁ The company expects a significant increase in licensing fee revenue in the second half of 2024 as customer projects restart. ➂ The royalty revenue is also expected to grow as chips begin mass production. ➃ Despite previous losses due to increased research and development expenses, Jianxin Technology is expected to achieve profitability in the fourth quarter of 2024.

➀ Scientists have created a flexible, programmable chip not made of silicon; ➁ The chip operates while bent and can run machine learning workloads; ➂ The microchip's open-source RISC-V architecture suggests it might cost less than a dollar; ➃ The chip could power wearable healthcare electronics, smart package labels, and other inexpensive items; ➄ The chip is based on the RISC-V instruction set and is programmable, running compiled programs in high-level languages; ➅ Flex-RV microprocessors can run as fast as 60 kilohertz while consuming less than 6 milliwatts of power; ➆ The researchers found that Flex-RV could still execute programs correctly when bent to a curve with a radius of 3 millimeters; ➇ The scientists detailed their findings in the journal Nature.

➀ The Zijing M100 chip, the first domestic RISC-V-based microcontroller chip with the highest level of localization, was successfully lit up on September 20th, marking a significant breakthrough for Great Wall Motors in the chip industry. The chip, developed by Great Wall Motors, is designed for automotive use, featuring high performance and an autonomous intellectual property. It is set to be integrated into multiple models and is expected to be installed in over 2.5 million vehicles within five years. ➁ The chip's successful lighting represents a substantial step in China's path to chip localization, contributing to the intelligent development of the automotive industry and the pursuit of self-reliance in technology. ➂ Great Wall Motors plans to establish a chip R&D company in Nanjing Research and Innovation Park, leveraging the Chinese Academy of Sciences' Institute of Computing Technology to develop automotive MCU function chips and high-performance chips.

➀ SiFive推出针对加速高性能AI工作负载的XM系列；➁ XM系列是SiFive的第一个包含可扩展AI矩阵引擎的IP，旨在加速边缘物联网、消费设备、下一代电动/自动驾驶汽车、数据中心等领域的芯片解决方案上市时间；➂ XM系列采用SiFive Kernel Library (SKL)的开源参考实现，提供高效的内存带宽。

➀ Intel is facing a major talent exodus with high-level employees leaving the company rapidly; ➁ Habana Labs co-founders David Dahan and Ran Halutz have left Intel to start an AI startup named Touch; ➂ Four senior CPU engineers from Intel have also left to found a new RISC-V core IP development company named Ahead Computing Inc.

➀ The popularity of RISC-V is rising, with industry giants like Intel, STMicroelectronics, and others investing in RISC-V startups; ➁ RISC-V is seen as a foundational technology for the digital infrastructure of the AI era, offering simplicity, openness, flexibility, low power consumption, modularity, and scalability; ➂ RISC-V is expected to become the native computing architecture for the AI era, with a significant market opportunity in the digital infrastructure sector.

➀ Nee Guohua emphasized that the integration of RISC-V and Chiplet will promote the innovation of DSA (Domain Specific Architecture) and lead to the 'Hardware Defined by Demand' era; ➁ The level of China's chip design has reached the world's advanced level in digital chips, but there is still a gap in analog chips; ➂ Scientists must not only have solid professional knowledge but also be brave in innovation and willing to take responsibility; ➃ RISC-V, as an emerging open instruction set architecture, is gaining global attention and is expected to promote innovation with its openness, efficiency, flexibility, low power consumption, modularity, and scalability; ➄ Chiplet technology, which encapsulates multiple pre-designed small chips into a complete SoC, is introduced to lower design complexity and cost while improving performance and flexibility; ➅ DSA (Domain Specific Architecture) computing architecture, characterized by customized design to better meet specific needs, shows great potential in emerging fields such as AI and IoT; ➆ The integration of RISC-V, extended instruction sets, Chiplet, and interconnect technologies in DSA new servers is expected to replace traditional X86 servers in terms of cost-performance and energy consumption, thus promoting the transformation and development of the Chinese server market; ➇ In the new era of 'Hardware Defined by Demand', hardware design will no longer rely solely on traditional standardized and generalized approaches but will be more closely integrated with actual application needs.

➀ The Orange Pi RV is a single-board computer featuring a RISC-V processor, making it one of the first in the Orange Pi lineup to adopt this architecture. ➁ It measures 89 x 56mm and is powered by a 1.5 GHz StarFive JH7110 processor with up to 8GB of LPDDR4-2800 memory. ➂ The board includes a variety of ports and connectors such as 4 USB 3.0, 1 USB 2.0 Type-C, HDMI, and Gigabit Ethernet, along with support for WiFi 5 and Bluetooth 5.

➀ ST has joined Quintauris, a RISC-V facilitator, as its sixth shareholder. ➁ Quintauris aims to advance the adoption of RISC-V-based products. ➂ Initial applications will focus on the automotive sector, with plans to expand to mobile and IoT.

➀ Four senior Intel CPU experts have left to form a RISC-V startup called AheadComputing. ➁ The team, with over 80 years of combined experience at Intel, aims to develop open specification core IP. ➂ AheadComputing could be an attractive acquisition target for companies like AMD.

➀ SiFive and PQShield have partnered to integrate post-quantum cryptography into SiFive’s high-performance processor families. ➁ This collaboration aims to protect critical systems from quantum attacks and accelerate the adoption of NIST's post-quantum cryptography standards on RISC-V technologies. ➂ The integration of PQShield’s PQPlatform-CoPro technology with SiFive’s processors ensures quantum-resistant hardware security and compliance with NIST standards without compromising performance.

➀ Jesse Taube has successfully ported RISC-V NOMMU Linux to the RP2350, a Raspberry Pi variant. ➁ The code is available on GitHub for use on the SparkFun Pro Micro – RP2350. ➂ This development opens up new possibilities for running Linux on RISC-V-based microcontrollers.

➀ RISC-V architecture manages to run The Witcher 3 at 15 FPS using emulation layers. ➁ The achievement is significant for the future of open-source architecture in gaming. ➂ Challenges remain in translating x86 instructions to RISC-V, affecting performance.

➀ The Witcher 3 becomes the first AAA game to run on an RISC-V machine using Box64, Wine, and DXVK. ➁ Challenges included limited OpenGL support and the need for more x86 instructions in RISC-V. ➂ Progress was made with the introduction of devices like the Milk-V Pioneer and the SpacemiT K1/M1 SoC, which support RISC-V Vector Extension (RVV). ➃ RISC-V still lacks certain critical instructions for efficient x86 emulation compared to other architectures. ➄ Despite limitations, The Witcher 3 runs at up to 15 fps in-game and full speed on the main menu on RISC-V hardware.

➀ Tenstorrent unveiled its Blackhole silicon at Hot Chips 2024, featuring a standalone AI computer based on Ethernet. ➁ The Blackhole chip includes sixteen RISC-V cores in four clusters, with additional 'baby' RISC-V cores for compute, data movement, and storage. ➂ It supports 10x 400Gbps Ethernet and 512GB/s of bandwidth, emphasizing data locality and minimizing off-chip DRAM usage. ➃ The architecture leverages Ethernet for scaling, avoiding the need for specialized interconnects like NVLink or InfiniBand. ➄ TT-Metalium is introduced as part of the low-level programming model to facilitate AI operations on the hardware.

➀ DeepComputing introduces the DC-ROMA RISC-V Pad II, a tablet powered by a RISC-V 64-bit 8-core CPU. ➁ The device supports Ubuntu 24.04 and Android 15, with options for up to 16GB RAM and 128GB storage. ➂ This tablet aims to facilitate mobile app development for the RISC-V architecture, especially beneficial for Chinese companies facing U.S. hardware restrictions.

➀ Four senior CPU architects from Intel, with a combined experience of over 80 years, have founded AheadComputing, a RISC-V technology startup. ➁ The founders, Debbie Marr, Mark Dechene, Jonathan Pearce, and Srikanth Srinivasan, have extensive experience in CPU architecture and microarchitecture. ➂ AheadComputing aims to develop attractive open-specification core IP and is currently recruiting talent with CPU design and verification experience.