➀ Jesse Taube has successfully ported RISC-V NOMMU Linux to the RP2350, a Raspberry Pi variant. ➁ The code is available on GitHub for use on the SparkFun Pro Micro – RP2350. ➂ This development opens up new possibilities for running Linux on RISC-V-based microcontrollers.

➀ RISC-V architecture manages to run The Witcher 3 at 15 FPS using emulation layers. ➁ The achievement is significant for the future of open-source architecture in gaming. ➂ Challenges remain in translating x86 instructions to RISC-V, affecting performance.

➀ The Witcher 3 becomes the first AAA game to run on an RISC-V machine using Box64, Wine, and DXVK. ➁ Challenges included limited OpenGL support and the need for more x86 instructions in RISC-V. ➂ Progress was made with the introduction of devices like the Milk-V Pioneer and the SpacemiT K1/M1 SoC, which support RISC-V Vector Extension (RVV). ➃ RISC-V still lacks certain critical instructions for efficient x86 emulation compared to other architectures. ➄ Despite limitations, The Witcher 3 runs at up to 15 fps in-game and full speed on the main menu on RISC-V hardware.

➀ Tenstorrent unveiled its Blackhole silicon at Hot Chips 2024, featuring a standalone AI computer based on Ethernet. ➁ The Blackhole chip includes sixteen RISC-V cores in four clusters, with additional 'baby' RISC-V cores for compute, data movement, and storage. ➂ It supports 10x 400Gbps Ethernet and 512GB/s of bandwidth, emphasizing data locality and minimizing off-chip DRAM usage. ➃ The architecture leverages Ethernet for scaling, avoiding the need for specialized interconnects like NVLink or InfiniBand. ➄ TT-Metalium is introduced as part of the low-level programming model to facilitate AI operations on the hardware.

➀ DeepComputing introduces the DC-ROMA RISC-V Pad II, a tablet powered by a RISC-V 64-bit 8-core CPU. ➁ The device supports Ubuntu 24.04 and Android 15, with options for up to 16GB RAM and 128GB storage. ➂ This tablet aims to facilitate mobile app development for the RISC-V architecture, especially beneficial for Chinese companies facing U.S. hardware restrictions.

➀ Four senior CPU architects from Intel, with a combined experience of over 80 years, have founded AheadComputing, a RISC-V technology startup. ➁ The founders, Debbie Marr, Mark Dechene, Jonathan Pearce, and Srikanth Srinivasan, have extensive experience in CPU architecture and microarchitecture. ➂ AheadComputing aims to develop attractive open-specification core IP and is currently recruiting talent with CPU design and verification experience.

➀ Akeana, backed by top investors, officially launches with a range of customizable RISC-V IP solutions. ➁ The company introduces three processor lines and SoC IP, ready for customer delivery. ➂ Akeana also offers an AI Matrix computation engine designed for AI acceleration.

➀ Introduces the CC2560A, the world's first RISC-V core super SIM chip, designed for multi-interface, high-security, and large-capacity smart card applications. ➁ Features a 32-bit RISC-V embedded security processor with a 120MHz clock speed, significantly enhancing transmission rates and computational power. ➂ Emphasizes advanced security measures including hardware-level encryption, EAL5+ certification, and support for international and national cryptographic algorithms.

➀ The Raspberry Pi Pico 2 features a price increase from $4 to $5, but offers enhanced functionalities including support for two processor architectures. ➁ The device maintains the same dimensions and GPIO configurations as its predecessor, with the microcontroller chip upgraded from RP2040 to RP2350 series, ensuring software and hardware compatibility. ➂ The RP2350 series microcontroller includes two Arm Cortex-M33 and two 32-bit Hazard3 RISC-V cores, allowing users to select which cores to use during the boot process.

➀ RISC-V's flexibility and scalability make it an ideal choice for AI chip design, allowing customization of AI accelerators. ➁ Two main models of RISC-V AI chips are identified: Integrated mode for low power and Attached mode for high computational power. ➂ Challenges in the RISC-V+AI ecosystem include fragmentation and insufficient resources, addressed through international standards and open-source software. ➃ Focus on edge computing and smart terminals to build a competitive software ecosystem against NVIDIA's CUDA. ➄ International collaboration and open-source community development are crucial for RISC-V's global market positioning.

➀ The Raspberry Pi Pico 2 features dual RISC-V Hazard3 cores, alongside Arm Cortex-M33 cores, selectable at boot time. ➁ It includes enhanced security features such as Arm TrustZone, signed boot, and hardware TRNG. ➂ The board supports both FreeRTOS and Zephyr operating systems, expanding its application possibilities.

➀ Raspberry Pi has introduced RISC-V cores on its new microcontroller, alongside Arm Cortex-M33 cores, making RISC-V more accessible. ➁ The new microcontroller, Proc0 and Proc1, can be independently set to either Arm Cortex-M33 or RISC-V core at boot. ➂ Raspberry Pi has also launched the Pico 2 development/application board to support the MCU, with additional boards featuring Wi-Fi, Bluetooth, or LoRa announced by other companies.

1. Akeana has announced its RISC-V processor intellectual property, featuring three series of cores. 2. The 100 Series includes configurable 32bit RISC-V cores for embedded microcontrollers. 3. The 1000 and 5000 Series offer 64bit RISC-V cores with advanced features for various applications including laptops, data centers, and cloud infrastructure.

1. Microchip has introduced its first 64-bit processors using the RISC-V instruction set, including an octa-core for space and a quad-core for industrial applications. 2. The company plans to develop future PIC64 families based on both RISC-V and Arm architectures. 3. The PIC64-HPSC space processors are designed for high-performance space-flight computing, offering significant computational improvements and advanced security features.

1. BAE Systems and GlobalFoundries collaborate on secure chip fabrication for aerospace and defense. 2. Europe launches a pilot line for 10nm and 7nm FD-SOI ICs. 3. SiFive introduces its 4th generation RISC-V CPU cores. 4. A startup, Etched, develops AI chips faster than Nvidia's Blackwell. 5. The automotive semiconductor market shows signs of slowing down.

1. SiFive, a leader in RISC-V computing, has announced the fourth generation of its popular Essential product line at the RISC-V Summit Europe 2024. 2. The Essential IP, developed over a decade, is already utilized in billions of products across various sectors including mobile phones, sensors, and smartwatches. 3. This update introduces enhanced performance, improved power efficiency, and more flexible interfaces to further spur innovation in embedded applications.

1. SiFive announced the 4th generation of RISC-V CPU cores for embedded applications at the RISC-V Summit Europe 2024. 2. The new cores include eight models, with three 32bit and five 64bit variants. 3. SiFive claims up to 40% runtime power reduction compared to its third generation, achieved through various optimizations and new power management features.

1. Framework has partnered with DeepComputing to develop a RISC-V mainboard for the Framework Laptop 13. 2. The prototype board features the StarFive JH7110 SoC. 3. It is set to be unveiled at the upcoming RISC-V Summit Europe event.