Recent #Arm news in the semiconductor industry

about 1 year ago
➀ The Raspberry Pi Pico 2 features a price increase from $4 to $5, but offers enhanced functionalities including support for two processor architectures. ➁ The device maintains the same dimensions and GPIO configurations as its predecessor, with the microcontroller chip upgraded from RP2040 to RP2350 series, ensuring software and hardware compatibility. ➂ The RP2350 series microcontroller includes two Arm Cortex-M33 and two 32-bit Hazard3 RISC-V cores, allowing users to select which cores to use during the boot process.
ArmRISC-VRaspberry Pi
about 1 year ago
➀ Intel has sold its 1.18 million Arm shares for approximately $145 million to reduce costs and strengthen its financial position. ➁ The sale comes as Intel faces liabilities of $32 billion and cash reserves of $11.3 billion as of June. ➂ The company has also announced plans to lay off at least 15% of its workforce, around 15,000 employees, to save $10 billion.
ArmFinanceIntel
over 1 year ago
1. Defacto Technologies and ARM have developed a joint SoC design flow using Arm IP Explorer and Defacto’s SoC compiler. 2. This automated approach significantly reduces manual effort and speeds up the design process. 3. Defacto's tools support configuration with RISC-V cores and scripting languages like Python, Tcl, Java, Ruby, and C++. 4. The company's EDA spinout, Innova, predicts EDA license and compute resource needs using an AI engine.
ArmSoC
over 1 year ago
1. Defacto and Arm have jointly developed an SoC design flow to automate the process from architecture exploration to top-level file generation for implementation and verification. 2. The solution integrates Arm IP Explorer and Defacto’s SoC Compiler, enabling quick generation of multiple SoC configurations and significantly reducing design time. 3. This solution is targeted at Arm users who need to rapidly build new Arm-based SoC configurations, enhancing efficiency and reducing costs and time to market.
ArmDefactoSoC Design
over 1 year ago
1. ARM has introduced a concept called High Bandwidth Instance (HBI) at the VLSI Symposium 2024, featuring an 8T 1R1RW SRAM design that allows for simultaneous read and write operations. 2. The HBI includes a DDATA memory that simplifies the design of the L1 Data Cache and offers a latency advantage of 10 to 15 ps. 3. ARM has tested a 3 nm chip with 112 SRAM-HBI macro cells, achieving speeds of up to 7.74 GHz at 0.945 V and 3.13 GHz at 0.495 V.
ArmHigh-Bandwidth-InstanceSRAM
over 1 year ago
1. Arm introduces the Ethos-U85 NPU, which boosts performance fourfold and enhances power efficiency. 2. The NPU supports complex machine learning applications and AI frameworks like TensorFlow Lite and PyTorch. 3. It is designed for applications such as factory automation and smart cameras, supporting advanced AI technologies like Transformer Networks and Convolutional Neural Networks.
ArmIoTNPUs
over 1 year ago

How much can running on a multi-core (Arm) CPU speed up fault simulation? Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is FaultRead More

The post Fault Sim on Multi-Core Arm Platform in China. Innovation in Verification appeared first on SemiWiki.

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