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  • The SemiWiki DAC#62 Preview

    ➀ The 62nd Design Automation Conference (DAC) will be held in San Francisco with over 6,000 participants, featuring a new Chiplet Pavilion and AI-focused discussions in EDA;

    ➁ Keynotes and panels will explore AI-driven electronic design cost reduction, with experts from NVIDIA and ChipAgents sharing insights;

    ➂ SemiWiki will provide live coverage and host panels, highlighting technologies like AgenticAI that aim to transform chip verification.

    EDAChipletAI

June 1

  • CEO Interview with Kit Merker of Plainsight

    ➀ Plainsight introduces OpenFilter, an open-source framework that simplifies large-scale computer vision deployment through containerized modular applications;

    ➁ The platform excels in retail, logistics, and manufacturing sectors with capabilities in object detection, real-time streaming (RTSP), and IoT integration;

    ➂ Differentiates through a unique filter abstraction technology that reduces development costs by 60% and enables seamless scaling from prototypes to production systems

    AIsoftwareHPC
  • CEO Interview with Bjorn Kolbeck of Quobyte

    ➀ Quobyte is a massively scalable storage system built on hyperscaler principles, capable of handling thousands of nodes on commodity hardware with fault-tolerant architecture;

    ➁ It excels in AI, HPC, and sectors like EDA/life sciences, offering hybrid cloud support and a unified file-object namespace to eliminate data silos;

    ➂ Differentiates through extreme simplicity of deployment (production-ready in <1 hour) and cost-efficiency compared to complex appliance-based competitors.

    HPCEDAAI

May 29

  • Synopsys Addresses the Test Barrier for Heterogeneous Integration

    ➀ Heterogeneous chip design faces multidimensional challenges requiring holistic solutions balancing architecture, verification, and testing;

    ➁ High-speed testing becomes critical for chiplet-based AI/HPC designs, demanding innovative approaches to overcome GPIO bandwidth limitations;

    ➂ Synopsys introduces HSGPIO technology enabling 10x faster test throughput without additional hardware, supporting multi-mode configurability for manufacturability and debug.

    SynopsysHPCAI chip
  • Anirudh Keynote at CadenceLIVE 2025 Reveals Millennium M2000

    ➀ Cadence unveiled the Millennium M2000 AI supercomputer platform powered by NVIDIA Blackwell, targeting acceleration in chip design, computational fluid dynamics, and biosciences;

    ➁ Announced a moonshot initiative to achieve full autonomy in chip design through agentic AI, guided by an automotive-inspired SAE autonomy framework;

    ➂ Expanded digital twin applications beyond semiconductors to data centers, robotics, and aerospace, leveraging partnerships with NVIDIA and Google.

    NVIDIAAI chipDigital Twins

May 28

  • Semiconductor Market Uncertainty

    ➀ Q1 2025全球半导体市场营收达1677亿美元,同比增18.8%,但环比降2.8%,头部企业表现分化:NVIDIA增12%,而铠侠降超20%;

    ➁ 关税不确定性导致Q2展望复杂,SK海力士预计增14.6%,铠侠则预降10.7%,AI需求持续支撑存储与GPU市场;

    ➂ 2025年全球半导体增长预测存分歧(7%-14%),IDC预计服务器/PC增速放缓,IMF因关税下调全球GDP至2.8%,产业链或延续低增长至2026年。

    NVIDIASK hynixAI
  • Design-Technology Co-Optimization (DTCO) Accelerates Market Readiness of Angstrom-Scale Process Technologies

    ➀ DTCO has transformed into a predictive strategy enabling co-development of process and design, exemplified by Synopsys' collaboration with Intel on 18A technology;

    ➁ Key advancements include RibbonFET alignment and PowerVia optimization, boosting design productivity and power efficiency in Intel’s 18A process;

    ➂ Synopsys’ PICO framework expands DTCO’s scope, ensuring full-stack optimization and enabling faster market readiness through pre-silicon validation.

    IntelSynopsysDTCO
  • Optimizing an IR for Hardware Design. Innovation in Verification

    ➀ LLHD, a multi-level intermediate representation (IR) for hardware design, aims to bridge high-level languages and machine code, offering optimization opportunities across EDA workflows;

    ➀ Cadence’s Paul Cunningham highlights LLHD’s potential for academic research but notes challenges in commercial adoption due to maturity barriers;

    ➂ Raúl Camposano acknowledges LLHD’s alignment with open-source compiler innovations but questions its scalability compared to software ecosystems.

    EDAHPCsoftware

May 27

  • WEBINAR: PCIe 7.0? Understanding Why Now Is the Time to Transition

    ➀ PCIe 7.0 achieves 128 GT/s bandwidth with PAM4 signaling and enhanced error correction, extending the innovations of PCIe 6.0;

    ➁ Key challenges involve managing multiple data movers and link layers, favoring bifurcation and dual-port interfaces over ultra-high clock speeds;

    ➂ PCIe 7.0 provides SoC designers flexibility for AI/HPC systems due to its cost-efficiency and low pin count compared to parallel buses.

    SynopsysPCIeHPC
  • Andes Technology: Powering the Full Spectrum – from Embedded Control to AI and Beyond

    ➀ Andes Technology offers a comprehensive RISC-V processor portfolio spanning embedded control, AI/ML acceleration, and high-performance computing (HPC), with cores ranging from ultra-low-power D23 to Linux-capable multicore AX60;

    ➁ The AndesAIRE platform enables tailored AI inference engines through automated custom instructions and RISC-V vector extensions, with deployments in Meta's recommendation systems and EdgeQ's 5G chips;

    ➂ Automotive-grade ISO 26262 ASIL-D certified processors and cybersecurity applications with Cornami's FHE solutions demonstrate cross-industry adoption, cementing Andes' 30% RISC-V market leadership.

    RISC-VAI chipHPC

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