➀ Alchip presents at TSMC OIP Ecosystem Forum; ➁ Challenges in 3D IC design overcome; ➂ Collaboration with Synopsys and TSMC for 3D design innovation
Recent #Chiplet news in the semiconductor industry
➀ Mixel's MIPI IP customer, Hercules Microelectronics, creates innovative MIPI solutions for dual-display foldable devices; ➁ Offloading foldable display tasks to an external dual display controller to save power and reduce complexity; ➂ Hercules Microelectronics’ HME-H3 FPGA, integrated with Mixel’s MIPI IP, provides a low-power solution for dual-display devices.
➀ The Nuclear Safety and Environmental Engineering Technology Institute at the China National Nuclear Corporation (CNNC) has achieved a significant milestone by successfully mass-producing a new chip. ➁ This breakthrough represents a major advancement in China's semiconductor industry. ➂ The new chip is set to enhance the nation's technological capabilities and competitiveness in the global market.
➀ Qualcomm's dispute with Arm Holdings is highlighted; ➁ Arm's architectural license agreement with Qualcomm is terminated; ➂ The dispute reflects the challenges posed by tech giants' custom silicon designs to Arm.
➀ Sarcina Technology addresses the cost and complexity of 2.5D package design with Bump Pitch Transformers; ➁ BPT replaces expensive silicon TSV interposers with cost-effective RDLs; ➂ Sarcina's BPT aims to democratize 2.5D design for various applications like HPC and AI.
➀ Google is rumored to switch to TSMC's N3E process for Tensor G5; ➁ The report also clarifies that Google has chosen not to use 2nm technology for Tensor G6; ➂ The move could impact the competition in the AI and smartphone chip markets.
➀ The increasing complexity of chip design necessitates efficient debugging solutions for successful prototype verification; ➁ Prototyping plays a crucial role in chip verification by enabling real-world scenario testing and early customer demonstrations; ➂ S2C's Prodigy prototyping solution offers a comprehensive debugging platform with tools like real-time control software, design debugging software, Multi-Debug Module, and ProtoBridge co-simulation software.
➀ Analog Bits showcased its on-die sensing IP and power management solutions at TSMC OIP; ➁ The company highlighted its progress in 3nm and 2nm technology nodes; ➂ Collaborations with Arm were discussed, focusing on power management and clocking IPs.
➀ Arm is exploring the feasibility of running LLMs on mobile devices; ➁ Arm's optimization techniques for LLMs on mobile; ➂ The importance of practical use cases for LLMs in mobile devices
➀ TSMC's 3DBlox framework addresses complexities in 3DIC design; ➁ Innovations in 2024 focus on simplifying 3D design challenges; ➂ TSMC's strategies for managing electrical and physical constraints in 3DIC systems.
➀ CEA-Leti is developing optical interposers using silicon photonics; ➁ The new technology, called Starac, aims to reduce communication delays; ➂ Starac uses an ONoC for high-speed data transmission between chiplets without intermediate hops.
➀ UCIe standardizes chiplet communication, lowering barriers and fostering innovation. ➁ It enables specialized and customized solutions by allowing mix-and-match of chiplets from various vendors. ➂ UCIe supports custom silicon for AI applications, enhancing performance and efficiency.
➀ Hynix plans to start sampling HBM3e 16hi memory with 48 GB capacity per cube in H1 2025; ➁ HBM3e 16hi offers a high-capacity alternative before the production of HBM4 16hi; ➂ HBM3e 16hi can deliver a maximum capacity of 384 GB per system, surpassing NVIDIA’s Rubin at 288 GB; ➃ Transitioning from HBM3e to HBM4 will double the I/O count and increase die size, but the per-die capacity remains at 24 GB; ➄ HBM3e 16hi will adopt the Advanced MR-MUF stacking process for higher stack counts and computational bandwidth.
➀ Nvidia surpasses Apple in market capitalization for the second time this year; ➁ Nvidia's market cap surged by 214% in one year; ➂ Nvidia's focus on AI and GPU sales drives its growth; ➃ AMD's CDNA3-based MI325X and CDNA4-based MI355X could challenge Nvidia's market dominance.
➀ Researchers from Queen Mary University of London have developed new nanocomposite films from starch, offering a sustainable alternative to petroleum-based materials; ➁ The films are made from abundant natural polymer starch and highly conductive MXene, with potential applications in electronics and sensing; ➂ The nanocomposites can be tailored for various uses, including wearable technology and healthcare, and are biodegradable.
➀ The article discusses the use of laser-based alignment for 3D semiconductor chip manufacturing, achieving precision down to fractions of a nanometer. ➁ Traditional methods using microscopes are limited due to the gap between chip layers, whereas the laser-based method overcomes this by using concentric metalenses to project holograms. ➂ The technology could also benefit advanced displacement sensors and startups in the semiconductor field.
➀ Alchip has taped out a 2nm test chip; ➁ The company expects results by the first quarter of next year; ➂ Alchip is working with customers on high-performance 2nm ASIC development.
➀ TSMC is the leading player in the semiconductor industry.
➁ Advanced packaging is becoming a key technology path for chip performance improvement.
➂ TSMC is expected to become the largest packaging service provider with the rapid adoption of Chiplet architecture.
➃ TSMC has invested heavily in advanced packaging technology, with capacity set to grow significantly.
➄ TSMC's CoWoS, InFO, and SoIC technologies are driving the company's leadership in advanced packaging.
➅ TSMC is expanding its capacity to meet the increasing demand for advanced packaging.
➆ TSMC is also investing in optical packaging technology to meet the growing bandwidth needs.
➀ Arm's Total Design initiative has doubled in size within a year; ➁ Samsung Foundry, ADTechnology, and Rebellions collaborate on a 2nm AI processor; ➂ The AI CPU chiplet platform is designed for AI/ML training, cloud computing, and high-performance computing workloads.
➀ Chiplet technology breaks down components from a single system-on-chip (SoC) into multiple small chips (chiplets) with specific functions, and then interconnects them using advanced packaging technology to form a system-in-package (SiP). Advanced packaging technology enhances Chiplet design and performance in terms of interconnect density, signal transmission optimization, thermal performance improvement, reduction of process dependency, and heterogeneous integration, accelerating chip design and application deployment.
➁ With the continuous improvement of chip performance, Chiplet design requires higher signal transmission speed from the substrate. Traditional substrates struggle to meet this demand, but glass substrates offer faster signal transmission rates, lower dielectric losses, and higher interconnect density, providing faster signal transmission channels for Chiplet chips. Additionally, glass substrates have larger packaging sizes and good mechanical stability, allowing for more chiplets in the same area, facilitating large-scale integration of Chiplets and enabling more complex system-in-package designs to meet the performance requirements of high-performance computing and artificial intelligence.
➂ On October 18th at 19:30, the 11th 'Xing Xing Chiplet and Advanced Packaging Public Lecture' will feature a talk by Ma Xiaobo, President of Hunan YueMo Research Institute, titled 'Glass Substrate Chiplet Advanced Packaging and Multi-Physical Field Simulation'. Ma will discuss the prospects and industry status of Chiplet advanced packaging technology, share the application advantages of glass substrates in advanced packaging, and focus on multi-physical field simulation for glass substrate Chiplet advanced packaging and the application and future development trends of deep learning in advanced packaging simulation.