Recent #Samsung news in the semiconductor industry

over 1 year ago
1. Q1 DRAM revenues increased by 5.1% despite a fall in units, driven by contract ASP increases. 2. The Big Three in DRAM saw seasonal shipment declines but benefited from price increases. 3. Mobile DRAM prices rose the most due to strong sales of Chinese smartphones, while consumer DRAM had the lowest price rises.
DRAMMicronSamsung
over 1 year ago
1. Samsung is set to introduce a revolutionary technology that allows stacking High Bandwidth Memory (HBM) on CPUs or GPUs this year. 2. The SAINT-D HBM, a key component of this technology, is scheduled for a 2024 rollout. 3. This development paves the way for the integration of HBM4 with Samsung's SAINT-D interconnection and packaging technology.
HBMSAINT-DSamsung
over 1 year ago
1. Synopsys has certified its AI-driven digital and analog design flows on Samsung's 2nm SF2 process with multiple test chip tapeouts. 2. The collaboration enhances performance, power efficiency, and area optimization, and accelerates analog design migration for Samsung's latest Gate-All-Around (GAA) process technologies. 3. Synopsys and Samsung are closely collaborating on AI-driven flows to optimize design productivity and PPA, and to enable efficient analog design migration.
AI DesignSamsungSynopsys
over 1 year ago
This week Samsung Electronics and Synopsys announced that Samsung has taped out its first mobile system-on-chip on Samsung Foundry's 3nm gate-all-around (GAA) process technology. The announcement, coming from electronic design automation Synopsys, further notes that Samsung used the Synopsys.ai EDA suite to place-n-route the layout and verify design of the SoC, which in turn enabled higher performance. Samsung's unnamed high-performance mobile SoC relies on 'flagship' general-purpose CPU and GPU architectures as well as various IP blocks from Synopsys. SoC designers used Synopsys.ai EDA software, including the Synopsys DSO.ai to fine-tune design and maximize yields as well as Synopsys Fusion Compiler RTL-to-GDSII solution to achieve higher performance, lower power, and optimize area (PPA). And while the news that Samsung has developed a high-performance SoC using the Synopsys.ai suite is important, there is another, even more important dimension to this announcement: this means that Samsung has finally taped out an advanced smartphone application processor on its cutting-edge 3nm GAAFET process. Although Samsung Foundry has been producing chips on its GAA-equipped SF3E (3 nm-class, 'early' node) process for almost two years now, Samsung Electronics has never used this technology for its own system-on-chips for smartphones or other complex devices. To date, SF3E has been used mainly for cryptocurrency mining chips, presumably due to the inevitable early teething and yield issues that come with being the industry's first commercial GAAFET process. For now, Samsung isn't disclosing what specific process node is being used for the SoC; the official Samsung/Synposys announcement only notes that it's for a GAA process node. Along with their first-generation 3nm-class SF3E, Samsung Foundry has a considerably more sophisticated SF3 manufacturing technology that offers numerous improvements over SF3E, and is due to be used for mass production in the coming quarters. Given th
EDAGAASamsungSynopsys
over 1 year ago
As part of Samsung's Q1 earnings announcement, the company has outlined some of its foundry unit's key plans for the rest of the year. The company has confirmed that it remains on track to meeting its goal of starting mass production of chips on its SF3 (3 nm-class, 2nd Generation) technology in the second half of the year. Meanwhile in June, Samsung Foundry will formally unveil its SF2 (2 nm-class) process technology, which will offer a mix of performance and efficiency enhancements. Finally, the company the company is preparing a variation of its 4 nm-class technology for integration into stacked 3D designs. SF2 To Be Unveiled In June Samsung plans to disclose key details about its SF2 fabrication technology at the VLSI Symposium 2024 on June 19. This will be the company's second major process node based upon gate-all-around (GAA) multi-bridge channel field-effect transistors (MBCFET). Improving over its predecessor, SF2 will feature a 'unique epitaxial and integration process,' which will give the process node higher performance and lower leakage than traditional FinFET-based nodes (though Samsung isn't disclosing the specific node they're comparing it to). Samsung says that SF2 increases performance of narrow transistors by 29% for N-type and 46% for P-type, and wide transistors by 11% and 23% respectively. Moreover, it reduces transistor global variation by 26% compared to FinFET technology, and cuts product leakage by approximately 50%. This process also sets the stage for future advancements in technology through enhanced design technology co-optimization (DTCO) collaboration with its customers. One thing that Samsung has not mentioned in context of SF2 is backside power delivery, so at least for the moment, there is no indication that Samsung will be adopting this next-gen power routing feature for SF2. Samsung says that the design infrastructure for SF2 – the PDK, EDA tools, and licensed IP – will be finalized in the second quarter of 2024. Once this happe
2nmGAASamsung