Recent #Memory Chips news in the semiconductor industry
➀ Yangtze Memory Technologies (YMTC) is shipping a TLC NAND with 294 layers, 232 of which are active;
➁ The new device has the same number of active layers as the company's previous generation NAND;
➂ The reason for the increase in dummy layers is unclear.
➀ China-based memory maker ChangXin Memory Technologies (CXMT) began shipping DDR5 memory chips, but their die size is 40% larger than Samsung's;
➁ The larger die size is due to the use of less advanced chipmaking technology;
➂ CXMT's 16 Gb DDR5 die size is comparable to first-generation DDR5 chips;
➃ CXMT's DDR5 costs are likely higher than Micron, Samsung, and SK hynix;
➄ The large die size indicates CXMT is years behind in process technology compared to competitors.
➀ TSMC's HBM4 memory launch brings significant changes, with the most noticeable being the expansion of memory interfaces from 1024 to 2048 bits;
➁ TSMC revealed details about base die for HBM4 manufacturing using improved versions of its N12 and N5 processes at the 2024 European Technology Symposium;
➂ TSMC plans to adopt two different manufacturing processes, N12FFC+ and N5, for the first batch of HBM4 product packaging;
➃ TSMC is working with major HBM memory suppliers like Micron, Samsung, and SK Hynix to integrate HBM4 memory technology using advanced process nodes;
➄ TSMC's N12FFC+ process is suitable for achieving HBM4 performance, allowing memory manufacturers to build 12-Hi (48GB) and 16-Hi (64GB) stacks with over 2TB/s bandwidth;
➅ TSMC's N5 process will integrate more logic functions, reduce power consumption, and provide higher performance with very small interconnect spacing, enabling HBM4 direct 3D stacking on logic chips.