Recent #energy efficiency news in the semiconductor industry
➀ Stanford University is researching a hybrid memory that combines the density of DRAM with the speed of SRAM, funded by CHIPS and Science Act.
➁ The research is part of the California Pacific Northwest AI Hardware Center project, which will receive $16.3 million from the US Department of Defense.
➂ The team, led by H.S. Philip Wong, focuses on developing more energy-efficient hardware for AI, with memory being the core.
➃ The hybrid gain cell memory combines the small footprint of DRAM with the almost as fast speed of SRAM.
➄ The gain cell, similar to DRAM, uses a second transistor instead of a capacitor to store data, with the data stored as charge on the gate of the transistor.
➅ Reading signals are无损 in the gain cell, and the reading transistor provides gain to the storage transistor during reading.
➆ Liu and Wong's mixed gain cell memory, combining silicon read transistors with indium tin oxide write transistors, overcomes limitations and achieves a data retention time of over 5000 seconds.
➇ These hybrid storage cells can be integrated into logic chips, potentially changing the way memory is used in computers.