Recent #EUV Lithography news in the semiconductor industry

11 months ago
➀ Researchers at the Paul Scherrer Institute (PSI) have achieved 5 nm half-pitch line/space patterns using 13.5 nm EUV light, surpassing the theoretical maximum resolution of ASML’s high-NA EUV tool. ➁ The technique used, EUV interference lithography (EUV-IL), involves making two EUV beams interfere to create periodic images, previously achieving patterns down to 6 nm half-pitch. ➂ The study concludes that photons are not the limiting factor for resolution at this scale, shifting focus to developing new photoresist materials and optimizing existing platforms.
EUV LithographyPhotonsresearch
11 months ago
➀ Imec has released images of single-exposure patterns using ASML’s high-NA EUV scanner, showcasing logic structures down to a 9.5nm half-pitch. ➁ The patterns include 30nm center-to-center random vias and a DRAM-relevant pattern at P22nm pitch, demonstrating the readiness of the ecosystem for high-resolution EUV lithography. ➂ These patterns were created at the ASML-Imec High NA EUV Lithography Lab in Veldhoven, highlighting the potential of High NA EUV for single-print imaging of aggressively-scaled 2D features.
EUV LithographyImecsemiconductor