1. Jusung Engineering is developing ALD technology to reduce the number of steps in the EUV process. 2. The chairman of Jusung Engineering, Chul Joo Hwang, believes that stacking transistors will be the future of semiconductor development. 3. This approach is seen as necessary due to the limitations in scaling DRAM and logic chips, similar to how NAND stacks transistors.

1、TSMC 是 EUV lithography 的领导者，拥有最多的 EUV 工具安装基础。 2、TSMC 的 EUV 晶圆生产能力已经从 2019 年的 1 倍增加到 30 倍。 3、TSMC 通过在 pellicle技术上的创新，提高了 EUV reticles 的使用寿命和输出能力。

Intel has secured the majority of high-NA extreme ultraviolet (EUV) equipment that ASML is manufacturing up to the first half of next year, TheElec has learned,The Dutch fab equipment maker is manufacturing five units of the kit this year, which will all go to the US chipmaker, sources said.As ASML’

The latest significant development in EUV lithography technology is the arrival of High-NA systems. Theoretically, by increasing the numerical aperture, or NA, from 0.33 to 0.55, the absolute minimum half-pitch is reduced by 40%, from 10 nm to 6 nm. However, for EUV systems, we need to recognize that the EUV light (consisting … Read More The post Why NA is Not Relevant to Resolution in EUV Lithography appeared first on SemiWiki.

Samsung was considering applying metal oxide resist (MOR) during the extreme ultraviolet (EUV) lithography process for its next-generation DRAM, TheElec has learned.MOR is considered the next-generation photoresist (PR) to the chemically amplified resist (CAR) currently used in the lithography of ad

On Friday April 12^th Intel held a press briefing on their adoption of High NA EUV with Intel fellow and director of lithography Mark Phillips.

In 1976 Intel built Fab 4 in Oregon, the first Intel fab outside of California. With the introduction of 300mm Oregon became the only development site for Intel with large manufacturing, development,… Read More

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