➀ Rise Design Automation showcased a next-gen HLS methodology at DAC, blending SystemVerilog/C++/SystemC with AI-driven tools to boost design efficiency;

➁ Their platform integrates LLM-based AI advisors for code generation and verification acceleration, achieving 100X-1,000X faster verification through high-level abstraction;

➂ The solution enables multi-language design exploration, automated testbench creation, and interoperability with EDA tools like VCS and Open ROAD, targeting area/power/performance optimization.