Recent #Architecture news in the semiconductor industry

4 months ago

➀ Jim Keller discusses his early work at DEC and AMD, focusing on the K8 architecture and his contributions to x86-64 and HyperTransport.

➁ Keller's experience at startup SiByte, including the development of network processors and his involvement with Andy Bechtolsheim and Cisco.

➂ His transition to Broadcom and the challenges of working in a larger company like Intel, where he learned about methodology and abstraction layers in computer design.

➃ Keller's time at P.A. Semi and his role in designing PowerPC processors, leading to the acquisition by Apple.

➄ His journey at Apple, from the first iPhone chip to the A-series processors, and the focus on performance and power efficiency.

➅ His return to AMD and the development of the Zen architecture, addressing the company's challenges and working with Global Foundries and TSMC.

➆ His move to Tesla and the development of the Hardware 3 chip for autonomous driving, followed by his transition to Intel and the challenges of managing a large engineering team.

➇ His current role at Tenstorrent AI, focusing on AI processors and software, and the company's mission to build a general-purpose computing platform.

AMDAppleArchitectureTeslajim keller
8 months ago

➀ NVIDIA CEO Jensen Huang responds to the Intel-AMD 'x86 Alliance';

➁ Huang emphasizes the importance of keeping the x86 architecture alive;

➂ NVIDIA supports the alliance's efforts to ensure cross-compatibility between platforms;

➃ Huang acknowledges the need for the x86 segment to remain united for future development;

➄ The alliance aims to counter growing market competition;

➅ Intel and AMD's alliance is seen as a response to NVIDIA's influence in AI markets;

➆ The PC market is facing competition from ARM architecture and AI PC chips.

ArchitectureNVIDIA
9 months ago
➀ The Stream Multi-processor (SM) is the core module of the GPU, executing the entire Kernel Grid. ➁ SM consists of a SIMT front end and a SIMD back end, processing instructions in six stages: fetch, decode, issue, operand delivery, execute, and write back. ➂ SM supports instruction-level parallelism but not out-of-order execution, with each Warp executing the same instruction in SIMD mode.
ArchitectureGPUSM