➀ NextSilicon's Maverick-2 accelerator chip adopts a dataflow architecture, emphasizing FP64 compute performance for HPC applications, differentiating itself from NVIDIA's shift away from FP64.

➁ The chip utilizes HBM3e memory and optimizes ALU density by reducing traditional CPU overheads (e.g., branch prediction), while its software identifies computational hotspots for efficient offloading to the accelerator.

➂ Maverick-2 employs adaptive "Mill Cores" to reconfigure dataflow paths dynamically, enabling high parallelism and flexibility akin to FPGAs, with early adoption by Sandia National Lab for real-world deployment.