1. Blue Pearl Software is celebrating 20 years since its first showcase of ASIC and FPGA static verification at the 2004 Design Automation Conference. 2. The Visual Verification Suite has evolved to offer advanced verification tools for ASIC, FPGA, and IP RTL, including structural and formal linting, constraint generation, and analysis packages for glitches and clock domain crossings. 3. The suite also features a Management Dashboard for progress tracking and has partnered with Accellera to standardize CDC/RDC/Glitch intent capture, addressing the challenge of IP reuse in different verification environments.